PRELIMINARY
LH5324P00A
FEATURES
•
3,145,728 words
×
8 bit organization
(Byte mode)
1,572,864 words
×
16 bit organization
(Word mode)
•
Access time: 120 ns (MAX.)
•
Power consumption:
Operating: 440 mW (MAX.)
Standby: 1650
µW
(MAX.)
•
Static operation
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
Package: 44-pin, 600-mil SOP
DESCRIPTION
The LH5324P00A is a 24M-bit mask-programmable
ROM organized as 3,145,728
×
8 bits (Byte mode) or
1,572,864
×
16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
44-PIN SOP
CMOS 24M (3M
×
8/1.5M
×
16)
Mask-Programmable ROM
PIN CONNECTIONS
TOP VIEW
NC
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
OE
D
0
D
8
D
1
D
9
D
2
D
10
D
3
D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
20
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
GND
D
15
/A
-1
(LSB)
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
5324P00A-1
Figure 1. Pin Connections for SOP Package
5-307
LH5324P00A
PRELIMINARY
CMOS 24M Mask-Programmable ROM
A
20
44
A
19
43
A
18
2
A
17
3
A
16
34
A
15
35
A
14
36
ADDRESS BUFFER
DATA SELECTOR/OUTPUT BUFFER
A
13
37
A
12
38
A
11
39
A
10
40
A
9
41
A
8
42
A
7
4
A
6
5
A
5
6
A
4
A
3
A
2
9
7
8
ADDRESS DECODER
MEMORY
MATRIX
(3,145,728 x 8)
(1,572,864 x 16)
31 D
15
29 D
14
27 D
13
25 D
12
22 D
11
20 D
10
18 D
9
16 D
8
30 D
7
28 D
6
26 D
5
24 D
4
21 D
3
19 D
2
17 D
1
COLUMN SELECTOR
A
1
10
A
0
11
CE 12
CE
BUFFER
TIMING
GENERATOR
15 D
0
SENSE AMPLIFIER
OE 14
OE
BUFFER
BYTE 33
BYTE/WORD
SWITCHOVER
CIRCUIT
ADDRESS
BUFFER
31
A
-1
23
V
CC
13 32
GND
5324P00A-2
Figure 2. LH5324P00A Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
SIGNAL
PIN NAME
NOTE
A
–1
– A
20
D
0
– D
15
BYTE
CE
Address input
Data output
Byte/word mode switch
Chip Enable input
1
1
1
OE
V
CC
GND
NC
Output Enable input
Power supply (+5 V)
Ground
No connection
NOTE:
1. The D
15
/A
–1
pin becomes LSB address input (A
–1
) when the BYTE pin is set to be LOW in byte mode, and data output (D
15
) when set to
be HIGH in word mode.
5-308
CMOS 24M Mask-Programmable ROM
PRELIMINARY
LH5324P00A
TRUTH TABLE
CE
OE
BYTE
A
–1
(D
15
)
DATA OUTPUT
D
0
– D
7
D
8
– D
15
ADDRESS INPUT
LSB
MSB
SUPPLY
CURRENT
NOTE
H
L
L
L
L
X
H
L
L
L
X
X
H
L
L
X
X
–
L
H
High-Z
High-Z
D
0
– D
7
D
0
– D
7
D
8
– D
15
High-Z
High-Z
D
8
– D
15
High-Z
High-Z
–
–
A
0
A
–1
A
–1
–
–
A
20
A
20
A
20
Standby (I
SB
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
1
1
NOTE:
1. X = H or L; High-Z = High-impedance
When the address inputs become ’High’ to both A
19
and A
20
, the data outputs become ‘Unspecified’
since the data does not exist in this address area.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
Topr
Tstg
– 0.3 to +7.0
– 0.3 to V
CC
+ 0.3
– 0.3 to V
CC
+ 0.3
0 to +70
– 65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input ‘High’ voltage
Input ‘Low’ voltage
Output ‘High’ voltage
Output ‘Low’ voltage
Input leakage current
Output leakage current
Operating current
Standby current
Input capacitance
Output capacitance
V
IH
V
IL
V
OH
V
OL
| I
LI
|
| I
LO
|
I
CC1
I
CC2
I
SB1
I
SB2
C
IN
C
OUT
I
OH
= –400
µA
I
OL
= 2.0 mA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 150 ns
t
RC
= 1
µs
CE = V
IH
CE = V
CC
– 0.2 V
f = 1 MHz
T
A
= 25°C
2.2
– 0.3
2.4
V
CC
+ 0.3
0.8
0.4
10
10
80
70
3
300
10
10
V
V
V
V
µA
µA
mA
mA
µA
pF
pF
1
2
NOTES:
1. CE/OE = V
IH
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
5-309
LH5324P00A
PRELIMINARY
CMOS 24M Mask-Programmable ROM
AC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
120
120
120
60
5
50
50
ns
ns
ns
ns
ns
ns
ns
1
NOTE:
1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
Input reference level
Output reference level
Output load condition
0.4 V to 2.6 V
10 ns
1.5 V
1.5 V
1TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
5-310
CMOS 24M Mask-Programmable ROM
PRELIMINARY
LH5324P00A
t
RC
A
-1
- A
20
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
t
OE
(NOTE)
t
OHZ
t
OH
t
CHZ
D
0
- D
7
NOTE:
The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
, have concluded.
DATA VALID
5324P00A-3
Figure 3. Byte Mode (BYTE = V
IL
)
t
RC
A
0
- A
20
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
t
OE
(NOTE)
t
OHZ
t
OH
t
CHZ
D
0
- D
15
NOTE:
The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
, have concluded.
DATA VALID
5324P00A-4
Figure 4. Word Mode (BYTE = V
IH
)
5-311
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