LH532600
FEATURES
•
262,144 words
×
8 bit organization
(Byte mode)
131,072 words
×
16 bit organization
(Word mode)
•
Access time: 100 ns (MAX.)
•
Static operation
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550
µW
(MAX.)
•
Mask-programmable control pin:
Pin 1 = OE
1
/OE
1
/DC
•
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
48-pin, 10
×
20 mm
2
TSOP (Type I)
DESCRIPTION
The LH532600 is a 2M-bit mask-programmable ROM
organized as 262,144
×
8 bits (Byte mode) or 131,072
×
16 bits (Word mode) that can be selected by BYTE
input pin. It is fabricated using silicon-gate CMOS proc-
ess technology.
CMOS 2M (256K
×
8/128K
×
16) MROM
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
OE
1
/OE
1
/DC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
OE
D
0
D
8
D
1
D
9
D
2
D
10
D
3
D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
GND
D
15
/A
-1
(LSB)
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
532600-1
TOP VIEW
Figure 1. Pin Connections for DIP and
SOP Packages
1
LH532600
CMOS 2M MROM
48 PIN TSOP (Type I)
TOP VIEW
BYTE
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
GND
NC
NC
OE
1
/OE
1
/DC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
D
15
/A
-1
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
V
CC
GND
D
11
D
3
D
10
D
2
D
9
D
1
D
8
D
0
OE
GND
GND
NOTE:
Reverse bend available on request.
532600-2
Figure 2. Pin Connections for TSOP Package
2
CMOS 2M MROM
LH532600
A
16
32
A
15
33
A
14
34
A
13
35
A
12
36
A
11
37
A
10
38
A
9
A
8
A
7
A
6
39
40
2
3
29 D
15
MEMORY
MATRIX
(262,144 x 8)
(131,072 x 16)
ADDRESS DECODER
ADDRESS BUFFER
DATA SELECTOR/OUTPUT BUFFER
27 D
14
25 D
13
23 D
12
20 D
11
18 D
10
16 D
9
14 D
8
28 D
7
26 D
6
24 D
5
22 D
4
19 D
3
17 D
2
15 D
1
A
5
4
A
4
5
A
3
6
A
2
7
A
1
8
A
0
9
COLUMN SELECTOR
CE 10
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
13 D
0
OE 12
OE
1
/OE
1
/ 1
DC
OE
BUFFER
BYTE 31
BYTE/WORD
SWITCHOVER
CIRCUIT
ADDRESS
BUFFER
29
A
-1
NOTE:
Pin numbers apply to the 40-pin DIP or SOP.
21
V
CC
11 30
GND
532600-3
Figure 3. LH532600 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
SIGNAL
PIN NAME
NOTE
A
–1
– A
16
D
0
– D
15
BYTE
CE
Address input
Data output
Byte/word mode switch
Chip enable input
1
1
1
OE
OE
1
/OE
1
/DC
V
CC
GND
Output enable input
Output enable input
Power supply (+5 V)
Ground
2, 3
NOTES:
1. The D
15
/A
–1
pin becomes LSB address input (A
–1
) when the BYTE pin is set to be LOW in byte mode, and data output (D
15
) when set to
be HIGH in word mode.
2. Active levels of OE
1
/OE
1
/DC are mask-programmable. When DC is selected out of OE
1
/OE
1
/DC, it is fixed to an active level. Then it is
recommended to apply either V
IH
or V
IL
to the DC pin.
3. DC = Don’t care.
3
LH532600
CMOS 2M MROM
TRUTH TABLE
CE
OE
OE
1
/OE
1
BYTE
A
–1
(D
15
)
DATA OUTPUT
D
0
– D
7
D
8
– D
15
ADDRESS INPUT
LSB
MSB
SUPPLY CURRENT
H
L
L
L
L
L
X
H
X
L
L
L
X
X
L/H
H/L
H/L
H/L
X
X
X
H
L
L
X
X
X
–
L
H
High-Z
High-Z
High-Z
D
0
– D
7
D
0
– D
7
D
8
– D
15
High-Z
High-Z
High-Z
D
8
– D
15
High-Z
High-Z
–
–
–
A
0
A
–1
A
–1
–
–
–
A
16
A
16
A
16
Standby
Operating
Operating
Operating
Operating
Operating
NOTE:
X = H or L, High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
Topr
Tstg
– 0.3 to +7.0
– 0.3 to V
CC
+ 0.3
– 0.3 to V
CC
+ 0.3
0 to +70
–65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input ‘High’ voltage
Input ‘Low’ voltage
Output ‘High’ voltage
Output ‘Low’ voltage
Input leakage current
Output leakage current
V
IH
V
IL
V
OH
V
OL
| I
Ll
|
| I
LO
|
I
CC1
I
OH
= – 400
µA
I
OL
= 2.0 mA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 100 ns
t
RC
= 1
µs
t
RC
= 100 ns
t
RC
= 1
µs
CE = V
IH
CE = V
CC
– 0.2 V
f = 1 MHz
T
A
= 25°C
2.2
– 0.3
2.4
V
CC
+ 0.3
0.8
V
V
V
0.4
10
10
75
65
70
60
3
100
10
10
V
µA
µA
mA
mA
mA
mA
mA
µA
pF
pF
1
2
2
3
3
Operating current
I
CC2
I
CC3
I
CC4
Standby current
Input capacitance
Output capacitance
I
SB1
I
SB2
C
IN
C
OUT
NOTES:
1. CE/OE/OE
1
= V
IH
, OE
1
= V
IL
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3. V
IN
= (V
CC
– 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
4
CMOS 2M MROM
LH532600
AC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
100
100
100
55
5
55
ns
ns
ns
ns
ns
ns
1
NOTE:
1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
Input/output reference level
Output load condition
0.4 to 2.6 V
10 ns
1.5 V
1 TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
5
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