LH53B16R00
FEATURES
•
1,048,576
×
16 bit organization
(Word mode: W = V
IL
)
524,288
×
32 bit organization
(Double Word mode: W = V
IH
)
•
Access time: 120 ns (MAX.)
Access time in page mode: 50 ns (MAX.)
•
Supply current:
– Operating: 180 mA (MAX.)
– Standby: 300
µA
(MAX.)
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
Static operation
•
Package:
70-pin, 500-mil SSOP
•
Others:
– Non programmable
– Not designed or rated as radiation
– hardened
– CMOS process (P type silicon
substrate)
DESCRIPTION
The LH53B16R00 is a 16M-bit CMOS mask ROM
(mask-programmable-read-only memory) organized as
1,048,576
×
16 bits (Word mode) or 524,288
×
32 bits
(Double Word mode). It is fabricated using silicon-gate
CMOS process technology.
CMOS 16M (1M
×
16/512K
×
32) MROM
PIN CONNECTIONS
70-PIN SSOP
A
0
A
1
A
2
A
3
A
4
A
5
V
CC
D
0
D
16
D
1
D
17
GND
V
CC
D
2
D
18
D
3
D
19
D
4
D
20
D
5
D
21
GND
V
CC
D
6
D
22
D
7
D
23
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
NC
NC
NC
W
OE
CE
GND
D
31
/A
-1
(NOTE)
D
15
D
30
D
14
GND
V
CC
D
29
D
13
D
28
D
12
D
27
D
11
D
26
D
10
GND
V
CC
D
25
D
9
D
24
D
8
V
CC
NC
A
18
A
17
A
16
A
15
A
14
A
13
TOP VIEW
NOTE:
D
31
/A
-1
pin becomes LSB address input (A
-1
) when the
W pin is set to be LOW in word mode, and data output
(D
31
) when set to be HIGH in double word mode.
53B16R00-1
Figure 1. Pin Connections
1
LH53B16R00
CMOS 16M (1M x 16/512K x 32) MROM
63 D
31
61 D
30
57 D
29
55 D
28
53 D
27
51 D
26
A
18
41
A
17
40
A
16
39
A
15
38
A
14
37
MEMORY
MATRIX
(1,048,576 x 16)
(524,288 x 32)
47
45
27
25
21
19
17
15
11
9
62
60
56
54
52
50
46
44
26
24
20
18
16
14
10
8
D
25
D
24
D
23
D
22
D
21
D
20
D
19
D
18
D
17
D
16
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
9
A
8
A
7
A
6
32
31
30
29
ADDRESS BUFFER
A
13
36
A
12
35
A
11
34
A
10
33
A
5
6
A
4
5
A
3
4
A
2
3
COLUMN SELECTOR
CE 65
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
OE 66
OE
BUFFER
12
22
DATA SELECTOR/OUTPUT BUFFER
ADDRESS DECODER
W 67
WORD/DOUBLE
WORD SWITCHOVER
CIRCUIT
ADDRESS
BUFFER
ADDRESS
BUFFER
28
49
59
64
7 13 23 43 48 58
V
CC
GND
63
A
-1
1
A
0
2
A
1
53B16R00-2
Figure 2. LH53B16R00 Block Diagram
2
CMOS 16M (1M x 16/512K x 32) MROM
LH53B16R00
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
-1
- A
1
A
2
- A
18
D
0
- D
31
W
Address input
(page mode operation)
Address input
Data output
×16
bit /
×32
bit
(word/double word)
mode select input
CE
OE
V
CC
GND
NC
Chip enable input
Output enable input
Power pin (+5 V)
Ground
No connection
TRUTH TABLE
CE
OE
W
A
-1
(D
31
)
DATA OUTPUT
D
0
- D
15
D
16
- D
31
ADDRESS INPUT
LSB
MSB
SUPPLY
CURRENT
H
L
L
L
L
X
H
L
L
L
X
X
H
L
L
X
X
L
H
High-Z
High-Z
D
0
- D
15
D
0
- D
15
D
16
- D
31
High-Z
High-Z
D
16
- D
31
High-Z
High-Z
A
0
A
-1
A
-1
A
18
A
18
A
18
Standby (I
SB
)
Operating
Operating
Operating
Operating
NOTE:
X = Don’t care; High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
T
OPR
T
STG
-0.3 to +7.0
-0.3 to V
CC
+ 0.3
-0.3 to V
CC
+ 0.3
0 to +70
-65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
3
LH53B16R00
CMOS 16M (1M x 16/512K x 32) MROM
DC ELECTRICAL CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0 to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input ‘High’ voltage
Input ‘Low’ voltage
Output ‘High’ voltage
Output ‘Low’ voltage
Input leakage current
Output leakage current
Operating current
Standby current
Input capacitance
Output capacitance
V
IH
V
IL
V
OH
V
OL
| I
LI
|
| I
LO
|
I
CC1
I
SB1
I
SB2
C
IN
C
OUT
I
OH
= -400
µA
I
OL
= 2.0 mA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 120 ns
CE = V
IH
CE = V
CC
- 0.2 V
f = 1 MHz, t
A
= 25°C
2.2
-0.3
2.4
V
CC
+0.3
0.8
0.4
10
10
180
2
300
10
10
V
V
V
V
µA
µA
mA
mA
µA
pF
pF
1
2
NOTES:
1. CE = V
IH
, OE = V
IH
, output is open
2. V
IN
= V
IH
, V
IL
, CE = V
IL
, output is open
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Page address access time
Output enable delay time
Output hold time
Output floating time
t
RC
t
AA
t
ACE
t
APA
t
OE
t
OH
t
CHZ
t
OHZ
120
5
120
120
50
50
40
40
ns
ns
ns
ns
ns
ns
ns
ns
1
NOTE:
1. Determined by the time for the output to be opened. (Irrespective of output voltage)
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input signal rise time
Input signal fall time
Input/output reference level
Output load condition
0.4 V to 2.6 V
10 ns
10 ns
1.5 V
1TTL + 100 pF
4
CMOS 16M (1M x 16/512K x 32) MROM
LH53B16R00
t
RC
A
-1
- A
18
(A
0
- A
18
)
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
t
OE
(NOTE)
t
OHZ
t
OH
t
CHZ
D
0
- D
15
(D
0
- D
31
)
NOTE:
The output data becomes valid when the
last intervals, t
AA
, t
ACE
, t
APA
, or t
OE
, have concluded.
DATA VALID
53B16R00-3
Figure 3. Read Cycle
A
2
- A
18
A
-1
- A
1
(A
0
- A
1
)
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
t
OE
(NOTE)
D
0
- D
15
(D
0
- D
31
)
DATA
VALID
DATA
VALID
DATA
VALID
DATA
VALID
t
OH
t
OH
t
OH
t
OH
t
OHZ
t
APA
(NOTE)
t
APA
(NOTE)
t
CHZ
NOTE:
The output data becomes valid when the
last intervals, t
AA
, t
ACE
, t
APA
, or t
OE
, have concluded.
53B16R00-4
Figure 4. Page Mode Read Cycle
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
