CY28547
Clock Generator for Intel
®
CK410M/CK505
Features
• Compliant to Intel
®
CK410M and CK505
• Selectable CPU frequencies
• Low power differential CPU clock pairs
• 100-MHz low power differential SRC clocks
• 96-MHz low power differential dot clock
• 27-MHz Spread and Non-spread video clock
• 48-MHz USB clock
• SRC clocks independently stoppable through
CLKREQ#[1:9]
Table 1. Output Confguration Table
CPU
x2/x3
SRC
x9/11
PCI
x5
REF
x2
DOT96
x1
USB_48M
x1
LCD
x1
27M
x2
• 96/100-MHz low power spreadable differential video
clock
• 33-MHz PCI clocks
• Buffered Reference Clock 14.318 MHz
• Low-voltage frequency select inputs
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
Block Diagram
VDD_REF
Pin Configuration
PLL Reference
VDD_CPU
CPUT[1:0]
CPUC[1:0]
CPU_STP#
PCI_STP#
CLKREQ#
FS[C:A]
ITP_EN
PLL1
CPU
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDD_SRC
SRCC_9
SRCT_9
VSS_SRC
CPUC2_ITP / SRCC_10
CPUT2_ITP / SRCT_10
VDDA
VSSA
* PGMODE
CPUC1_MCH
CPUT1_MCH
VDD_CPU
CPUC0
CPUT0
VSS_CPU
SCLK
SDATA
VDD_REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VDD_SRC
SRCC_2
SRCT_2
SRCC_1/SATAC
SRCT_1/SATAT
VDD_SRC
SRCC_0 / LCD100MC
SRCT_0 / LCD100MT
CLKREQ1#
FSB/TEST_MODE
DOT96C / 27M_SS
DOT96T / 27M_NSS
VSS_48
48M / FSA
VDD_48
VTT_PWRGD# / PD (CKPWRGD/PD#)
CLKREQ7#
PCIF0/ITP_SEL
Divider
VDD_SRC
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD_SRC
Divider
SRCT [9:1]
SRCC [9:1]
VDD_PCI
Divider
PCI[4:1]
VDD_PCI
PCIF0
VDD_SRC
PLL3
Graphi
c
FCTSEL
Divider
LCD_100MT/SRCT0
LCD_100MC/SRCC0
VDD_48
27_SS
VDD_48
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
XOUT
XIN
VSS_REF
REF1
REF0 / FSC_TEST_SEL
CPU_STP#
PCI_STP#
CLKREQ2#
PCI1
CLKREQ3#
CLKREQ5#
VDD_PCI
VSS_PCI
PCI2/TME
PCI3
PCI4 / FCTSEL1
VSS_PCI
VDD_PCI
PLL2
Fixed
Divider
DOT96T
DOT96C
VDD_48
USB_48 [1:0]
PLL4
27M
VTTPWR_GD#/PD
VDD_48
27_NSS
SDATA
SCLK
I2C
Logic
....................... Document #: 001-05103 Rev *B Page 1 of 24
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
CLKREQ9#
CLKREQ8#
SRCT_8
SRCC_8
VSS_SRC
SRCC_7
SRCT_7
VDD_SRC
SRCC_6
SRCT_6
CLKREQ6#
SCRC_5
SRCT_5
SCRC_4
SRCT_4
CLKREQ4#
SRCC_3
SRCT_3
Xin
Xout
14.318MHz
Crystal
REF[1:0]
CY28547
www.silabs.com
CY28547
Pin Description
Pin No.
2, 3, 52, 53,
55, 56, 58,
59, 60, 61,
63, 64, 66,
67, 69, 70
4, 68
5, 6
Name
SRCT/C[2:9]
Type
PWR
3.3V power supply for outputs.
Description
1, 49, 54, 65 VDD_SRC
O, DIF 100-MHz Differential serial reference clocks.
VSS_SRC
GND
Ground for outputs.
CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output.
CPUC2_ITP/SRCC10
ITP_SEL = 0 @ pin 39 assertion = SRC10
ITP_SEL = 1 @ pin 39 assertion = CPU2
VDDA
VSSA
PGMODE
PWR
GND
I, PU
3.3V power supply for PLL.
Ground for PLL.
3.3V LVTTL input for selecting the polarity of pin 39
Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low externally
if needed
7
8
9
PGMODE CLK mode Pin 39
0
1(default)
CK410
CK505
VTT_PWRGD#/PD
CK_PWRGD/PD#
10, 11
12
13, 14
15
16
17
18
19
20
21
22
23
CPUC1_MCH,
CPUT1_MCH
VDD_CPU
CPU[T/C]0
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
REF1
REF0/FSC_TESTSEL
O, DIF Differential CPU clock output to MCH
PWR
GND
I
PWR
I
GND
O
I/O
3.3V power supply for outputs.
Ground for outputs.
SMBus-compatible SCLOCK.
3.3V power supply for outputs.
14.318-MHz crystal input.
Ground for outputs.
Fixed 14.318-MHz clock output.
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to V
IMFS_C
when pin 39 is asserted LOW.
Refer to DC Electrical Specifications table for
V
ILFS_C
,V
IMFS_C
,V
IHFS_C
specifi-
cations.
3.3V LVTTL input for CPU_STP# active LOW
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on this pin and sampled on the rising edge of PCI_STP#. See Figure 14.for more
information.
3.3V LVTTL input for PCI_STP# active LOW
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STP# and sampled on the rising edge of this pin. See Figure 14. for more
information.
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
O, DIF Differential CPU clock output
I/O, OD SMBus-compatible SDATA.
O, SE 14.318-MHz crystal output.
24
CPU_STP#
I
25
PCI_STP#
I
26, 28, 29,
38, 46, 57,
62, 71, 72
27
30, 36
31, 35
CLKREQ[1:9]#
I
PCI1
VDD_PCI
VSS_PCI
O, SE 33MHz clock output
PWR
GND
3.3V power supply for outputs.
Ground for outputs.
.......................Document #: 001-05103 Rev *B Page 2 of 24
CY28547
Pin Description
(continued)
Pin No.
32
Name
PCI2/TME
Type
Description
I/O, SE 33-MHz clock output/Trusted Mode Enable Strap
Strap at pin 39 assertion to determine if the part is in trusted mode or not.
Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low externally
if needed
0 = Normal mode
1= Trusted mode (default)
O, SE 33-MHz clock output
I/O
33-MHz clock output/3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on pin 39 assertion).
Internal pull-down resistor of 100K to GND
33
34
PCI3
PCI4/FCTSEL1
FCTS E L1 P in 43
0 DOT96T
1 27M_NSS
P in 44
DOT96C
27M_SS
P in 47
SRCT0
P in 48
SRCC0
96/100M_T 96/100M_C
37
ITP_SEL/PCIF0
I/O,SE 3.3V LVTTL input to enable SRC10 or CPU2_ITP/33-MHz clock output. (sampled
on pin 39 assertion).
Internal pull-down resistor of 100K to GND
1 = CPU2_ITP, 0 = SRC10
I
3.3V LVTTL input. This pin is a level sensitive strobe. When asserted, according
to the polarity defined by pin 9 (PGMODE), it latches data on the FSA, FSB, FSC,
FCTSEL1 and ITP_SEL pins. After assertion, it becomes a real time input for
controlling power down.
39
VTT_PWRGD#/PD
CKPWRGD/PD#
PGMODE
0
0
1
1
Pin 39
0 = POWER GOOD (VTT_PWRGD#)
1 = POWER DOWN (PD)
0 = POWER DOWN (PD#)
1 = POWER GOOD (CKPWRGD)
40
41
42
43, 44
45
VDD_48
48M/FSA
VSS_48
DOT96T/ 27M_NSS
DOT96C/ 27M_SS
FSB/TEST_MODE
PWR
I/O
GND
3.3V power supply for outputs.
Fixed 48-MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output Selected
via FCTSEL1 at pin 39 assertion.
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when
in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
47, 48
SRC[T/C]0/
LCD100M[T/C]
SRCT_1/SATAT,
SRCC_1/SATAC
O,DIF 100-MHz differential serial reference clock output/Differential 96/100-MHz SS
clock for flat-panel display
Selected via FCTSEL1 at pin 39 assertion.
O, DIF 100-MHz Differential serial reference clocks.
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
50, 51
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
.......................Document #: 001-05103 Rev *B Page 3 of 24
CY28547
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 3.
The block write and block read protocol is outlined in
Table 4
while
Table 5
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
Table 2. Frequency Select Table FSA, FSB, and FSC
FSC
1
0
0
0
FSB
0
0
1
1
FSA
1
1
1
0
CPU
100 MHz
133 MHz
166 MHz
200 MHz
SRC
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
Table 3. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
Read = 1
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Block Read Protocol
Description
.......................Document #: 001-05103 Rev *B Page 4 of 24
CY28547
Table 4. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
Description
Bit
....
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Stop
Block Read Protocol
Description
Control Registers
Byte 0 Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
1
Name
RESEREVD
RESEREVD
RESEREVD
iAMT_EN
RESEREVD
RESEREVD
RESEREVD
PD_Restore
RESERVED
RESERVED
RESERVED
Set via SMBus or by combination of PD, CPU_STP and PCI_STP
0 = Legacy mode, 1 = iAMT enable
RESERVED
RESERVED
RESERVED
Save configuration in PD
0 = Configuration cleared, 1 = Configuration saved
Description
Byte 1 Control Register 1
Bit
7
6
5
4
3
@Pup
1
1
1
1
1
Name
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]7 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]6 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]5 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]4 Output Enable
0 = Disabled, 1 = Enabled
SRC[T/C]3 Output Enable
0 = Disabled, 1 = Enabled
Description
.......................Document #: 001-05103 Rev *B Page 5 of 24
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