LH540203
FEATURES
•
Fast Access Times: 15/20/25/35/50 ns
•
Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology
•
Input Port and Output Port Have Entirely
Independent Timing
•
Expandable in Width and Depth
•
Full, Half-Full, and Empty Status Flags
•
Data Retransmission Capability
•
TTL-Compatible I/O
•
Pin and Functionally Compatible with Sharp LH5498
and with Am/IDT/MS7203
•
Control Signals Assertive-LOW for Noise Immunity
•
Packages:
28-Pin, 300-mil PDIP
28-Pin, 300-mil SOJ *
32-Pin PLCC
CMOS 2048
×
9 Asynchronous FIFO
FUNCTIONAL DESCRIPTION
The LH540203 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS dual-port SRAM tech-
nology, capable of storing up to 2048 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540203 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.
The input and output ports operate entirely inde-
pendently of each other, unless the LH540203 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOW control inputs: Write (W) for data entry at the
input port, or Read (R) for data retrieval at the output port.
Full, Half-Full, and Empty status flags monitor the
extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional words into an already-full
LH540203, or by attempting to read additional words from
an already-empty LH540203. When an LH540203 is
operating in a depth-cascaded configuration, the Half-Full
Flag is not available.
PIN CONNECTIONS
NC
*
28-PIN PDIP
28-PIN SOJ
*
D
3
D
8
D
4
W
D
8
D
3
D
2
D
1
D
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D
4
D
5
D
6
D
7
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
540203-2D
4
D
2
D
1
D
0
XI
FF
Q
0
Q
1
NC
Q
2
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
D
6
D
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
14 15 16 17 18 19 20
NC
*
Q
3
V
SS
Q
8
R
Q
4
NOTE:
*
= No external electrical connections are allowed.
540203-3D
Figure 1. Pin Connections for PDIP and
SOJ * Packages
Figure 2. Pin Connections for PLCC Package
* This is a final data sheet; except that all references to the SOJ package have Advance Information status.
Q
5
D
5
W
TOP VIEW
32-PIN PLCC
V
CC
TOP VIEW
1
LH540203
CMOS 2048
×
9 Asynchronous FIFO
The Reset (RS) control signal returns the LH540203
to an initial state, empty and ready to be filled. An
LH540203 should be reset during every system power-up
sequence. A reset operation causes the internal FIFO-
memory-array write-address pointer, as well as the read-
address pointer, to be set back to zero, to point to the
LH540203’s first physical memory location. Any informa-
tion which previously had been stored within the
LH540203 is not recoverable after a reset operation.
A cascading (depth-expansion) scheme may be imple-
mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/HF) output signal. This allows a
deeper ‘effective FIFO’ to be implemented by using two
or more LH540203 devices, without incurring additional
latency (‘fallthrough’ or ‘bubblethrough’) delays, and with-
out the necessity of storing and retrieving any given data
word more than once. In this cascaded operating mode,
one LH540203 device must be designated as the ‘first-
load’ or ‘master’ device, by grounding its First-Load
(FL/RT) control input; the remaining LH540203 devices
are designated as ‘slaves,’ by tying their FL/RT inputs
HIGH. Because of the need to share control signals on
pins, the Half-Full Flag and the retransmission capability
are not available for either ‘master’ or ‘slave’ LH540203
devices operating in cascaded mode.
FUNCTIONAL DESCRIPTION (cont’d)
Data words are read out from the LH540203’s output
port in precisely the same order that they were written in
at its input port; that is, according to a First-In, First Out
(FIFO) queue discipline. Since the addressing sequence
for a FIFO device’s memory is internally predefined, no
external addressing information is required for the opera-
tion of the LH540203 device.
Drop-in-replacement compatibility is maintained with
both larger sizes and smaller sizes of industry-standard
nine-bit asynchronous FIFOs. The only change is in the
number of internally-stored data words implied by the
states of the Full Flag and the Half-Full Flag.
The Retransmit (RT) control signal causes the internal
FIFO-memory-array read-address pointer to be set back
to zero, to point to the LH540203’s first physical memory
location, without affecting the internal FIFO-memory-
array write-address pointer. Thus, the Retransmit control
signal provides a mechanism whereby a block of data,
delimited by the zero physical address and the current
write-address-pointer value, may be read out
repeatedly
an arbitrary number of times. The only restrictions are that
neither the read-address pointer nor the write-address
pointer may ‘wrap around’ during this entire process, i.e.,
advance past physical location zero after traversing the
entire memory. The retransmit facility is not available
when an LH540203 is operating in a depth-expanded
configuration.
RS
RESET
LOGIC
INPUT
PORT
CONTROL
WRITE
POINTER
DATA INPUTS
D
0
- D
8
OUTPUT
PORT
CONTROL
READ
POINTER
W
R
DUAL-PORT
RAM
ARRAY
2048 x 9
...
DATA OUTPUTS
Q
0
- Q
8
FLAG
LOGIC
EF
FF
FL/RT
XI
EXPANSION
LOGIC
XO/HF
540203-1
Figure 3. LH540203 Block Diagram
2
CMOS 2048
×
9 Asynchronous FIFO
LH540203
PIN DESCRIPTIONS
PIN
PIN TYPE
1
DESCRIPTION
PIN
PIN TYPE
1
DESCRIPTION
D
0
– D
8
Q
0
– Q
8
W
R
EF
FF
I
O/Z
I
I
O
O
Input Data Bus
Output Data Bus
Write Request
Read Request
Empty Flag
Full Flag
XO/HF
XI
FL/RT
RS
V
CC
V
SS
O
I
I
I
V
V
Expansion Out/Half-Full Flag
Expansion In
First Load/Retransmit
Reset
Positive Power Supply
Ground
NOTE:
1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
OPERATIONAL DESCRIPTION
Reset
The LH540203 is reset whenever the Reset input (RS)
is taken LOW. A reset operation initializes both the read-
address pointer and the write-address pointer to point to
location zero, the first physical memory location. During
a reset operation, the state of the XI and FL/RT inputs
determines whether the device is in standalone mode or
in depth-cascaded mode. (See Tables 1 and 2.) The reset
operation forces the Empty Flag EF to be asserted
(EF = LOW), and the Half-Full Flag HF and the Full Flag
FF to be deasserted (HF = FF = HIGH); the Data Out pins
(D
0
– D
8
) are forced into a high-impedance state.
A reset operation is required whenever the LH540203
first is powered up. The Read (R) and Write (W) inputs
may be in any state when the reset operation is initiated;
but they must be HIGH, before the reset operation is
terminated by a rising edge of RS, by a time t
RRSS
(for
Read) or t
WRSS
(for Write) respectively. (See Figure 10.)
Write
A write cycle is initiated by a falling edge of the Write
(W) control input. Data setup times and hold times must
be observed for the data inputs (D
0
– D
8
). Write opera-
tions may occur independently of any ongoing read op-
erations. However, a write operation is possible only if the
FIFO is not full, (i.e., if the Full Flag FF is HIGH).
At the falling edge of W for the first write operation after
the memory is half filled, the Half-Full Flag is asserted
(HF = LOW). It remains asserted until the difference
between the write pointer and the read pointer indicates
that the data words remaining in the LH540203 are filling
the FIFO memory to less than or equal to one-half of its
total capacity. The Half-Full Flag is deasserted
(HF = HIGH) by the appropriate rising edge of R. (See
Table 3.)
The Full Flag is asserted (FF = LOW) at the falling edge
of W for the write operation which fills the last available
location in the FIFO memory array. FF = LOW inhibits
further write operations until FF is cleared by a valid read
operation. The Full Flag is deasserted (FF = HIGH) after
the next rising edge of R releases another memory loca-
tion. (See Table 3.)
Read
A read cycle is initiated by a falling edge of the Read
(R) control input. Read data becomes valid at the data
outputs (Q
0
– Q
8
) after a time t
A
from the falling edge of
R. After R goes HIGH, the data outputs return to a
high-impedance state. Read operations may occur inde-
pendently of any ongoing write operations. However, a
read operation is possible only if the FIFO is not empty
(i.e., if the Empty Flag EF is HIGH).
The LH540203’s internal read-address and write-
address pointers operate in such a way that consecutive
read operations always access data words in the same
order that they were written. The Empty Flag is asserted
(EF = LOW) after that falling edge of R which accesses
the last available data word in the FIFO memory. EF is
deasserted (EF = HIGH) after the next rising edge of W
loads another valid data word. (See Table 3.)
Data Flow-Through
Read-data flow-through mode occurs when the Read
(R) control input is brought LOW while the FIFO is empty,
and is held LOW in anticipation of a write cycle. At the end
of the next write cycle, the Empty Flag EF momentarily is
deasserted, and the data word just written becomes
available at the data outputs (Q
0
– Q
8
) after a maxi-
mum time of t
WEF
+ t
A
. Additional write operations may occur
while the R input remains LOW; but only data from the
first write operation flows through to the data outputs.
Additional data words, if any, may be accessed only by
toggling R.
Write-data flow-through mode occurs when the Write
(W) input is brought LOW while the FIFO is full, and is
held LOW in anticipation of a read cycle. At the end of the
read cycle, the Full Flag momentarily is deasserted, but
then immediately is reasserted in response to W being
held LOW. A data word is written into the FIFO on the
rising edge of W, which may occur no sooner than
t
RFF
+ t
WPW
after the read operation.
3
LH540203
CMOS 2048
×
9 Asynchronous FIFO
Table 2. Expansion-Pin Usage According to
Grouping Mode
I/O
PIN
STANDALONE
OPERATIONAL DESCRIPTION (cont’d)
Retransmit
The FIFO can be made to reread previously-read data
by means of the Retransmit function. A retransmit opera-
tion is initiated by pulsing the RT input LOW. Both R and
W must be deasserted (HIGH) for the duration of the
retransmit pulse. The FIFO’s internal read-address
pointer is reset to point to location zero, the first physical
memory location, while the internal write-address
pointer remains unchanged.
After a retransmit operation, those data words in the
region in between the read-address pointer and the
write-address pointer may be reaccessed by subsequent
read operations. A retransmit operation may affect the
state of the status flags FF, HF, and EF, depending on
the relocation of the read-address pointer. There is no
restriction on the number of times that a block of data
within an LH540203 may be read out, by repeating the
retransmit operation and the subsequent read operations.
The maximum length of a data block which may be
retransmitted is 2048 words. Note that if the write-address
pointer ever ‘wraps around’ (i.e., passes location zero
more than once) during a sequence of retransmit opera-
tions, some data words will be lost.
The Retransmit function is not available when the
LH540203 is operating in depth-cascaded mode,
because the FL/RT control pin must be used for first-load
selection rather than for retransmission control.
Table 1. Grouping-Mode Determination
During a Reset Operation
XI
FL/
RT
MODE
XO/HF
XI
FL/RT
USAGE USAGE USAGE
CASCADED CASCADED
MASTER
SLAVE
I
XI
Grounded
From XO
(n-1st
FIFO)
To XI
(n+1st
FIFO)
Grounded
(Logic
LOW)
From XO
(n-1st
FIFO)
To XI
(n+1st
FIFO)
Logic
HIGH
O
XO/HF
Becomes
HF
Becomes
RT
I
FL/RT
Table 3. Status Flags
NUMBER OF UNREAD DATA
WORDS PRESENT WITHIN
2048
×
9 FIFO
FF
HF
EF
0
1 to 1024
1025 to 2047
2048
H
H
H
L
H
H
L
L
L
H
H
H
H
1
H
1
L
H
L
X
Cascaded
Slave
2
Cascaded
Master
2
Standalone
XO
XO
HF
XI
XI
(none)
FL
FL
RT
NOTES:
1. A reset operation forces XO HIGH for the n
th
FIFO, thus forcing
XI HIGH for the (n+1)
st
FIFO.
2. The terms ‘master’ and ‘slave’ refer to operation in depth-cas-
caded grouping mode.
3. H = HIGH; L = LOW; X = Don’t Care.
4
CMOS 2048
×
9 Asynchronous FIFO
LH540203
Width Expansion
Word-width expansion is implemented by placing mul-
tiple LH540203 devices in parallel. Each LH540203
should be configured for standalone mode. In this ar-
rangement, the behavior of the status flags is identical for
all devices; so, in principle, a representative value for
each of these flags could be derived from any one device.
In practice, it is better to derive ‘composite’ flag values
using external logic, since there may be minor speed
variations between different actual devices. (See Figures
4, 5, and 6.)
OPERATIONAL MODES
Standalone Configuration
When depth cascading is not required for a given
application, the LH540203 is placed in standalone mode
by tying the Expansion In input (XI) to ground. This
input is internally sampled during a reset operation. (See
Table 1.)
HF
WRITE
W
R
READ
DATA IN
D
0
- D
8
9
LH540203
9
DATA OUT
Q
0
- Q
8
FULL FLAG
FF
EF
EMPTY FLAG
RESET
RS
RT
RETRANSMIT
XI
540203-17
Figure 4. Standalone FIFO (2048
×
9)
DATA IN
D
0
- D
17
18
9
WRITE
FULL FLAG
RESET
W
FF
HF
9
W
R
LH540203
RS
RT
9
XI
RS
HF
EF
LH540203
R
EMPTY FLAG
READ
RT
9
XI
RETRANSMIT
18
DATA OUT
Q
0
- Q
17
540203-18
Figure 5. FIFO Word-Width Expansion (2048
×
18)
5
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