24LLC16
16K-Bit-Serial EEPROM
OVERVIEW
The 24LLC16 serial EEPROM has a 16 Kbits (2,048 bytes) capacity, supporting the standard I
2
C™-bus serial
interface. It is fabricated using CERAMATE’s most advanced CMOS technology. One of its major features is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into
the EEPROM in a single write operation. Another significant feature of the 24LLC1616 is its support for fast
mode and standard mode.
FEATURES
I
2
C-Bus Interface
•
•
Two-wire serial interface
Automatic word address increment
Operating Characteristics
•
•
Operating voltage: 2.0 V to 5.5 V
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200
µA
at 5.5 V
— Maximum stand-by current: < 2
µA
at 2.0 V
•
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
•
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
•
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 400 V (MM)
Packages
•
8-pin DIP, SOP, and TSSOP
EEPROM
•
•
•
•
•
•
•
16 Kbits (2,048 bytes) storage area
16-byte page buffer
Typical 3 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
ORDERING INFORMATION
24 LLC
16
X
X
Operating Voltage
LLC:2.0~5.5V,CMOS
Type
16=16K
Temp. grade
Blank:-25℃~+70℃
Packing
Blank :Tube
A :Taping(SOP8)
T :Taping(TSSOP8)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 1 of 22
Rev 1.0 Aug.5, 2002
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24LLC16
16K-Bit-Serial EEPROM
SDA
Start/Stop
Logic
HV Generation
Timing Control
WP
Control Logic
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
EEPROM
Cell Array
2,048 x 8 bits
A0
A1
A2
Column Decoder
Data Register
D
OUT
and ACK
Figure 5-1. 24LLC16 Block Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 2 of 22
Rev 1.0 Aug.5, 2002
Fax:886-3-3521052
24LLC16
16K-Bit-Serial EEPROM
V
CC
WP
SCL SDA
24LLC16
A0
A1
A2
V
SS
NOTE:
The 24LLC16 is available in
8-pin DIP, SOP, and TSSOP package.
Figure 5-2. Pin Assignment Diagram
Table 5-1. 24LLC16 Pin Descriptions
Name
A0, A1, A2
V
SS
SDA
Type
–
–
I/O
No internal connection
Ground pin.
Bi-directional data pin for the I
2
C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor
must be connected to V
DD.
Schmitt trigger input pin for serial clock input.
Input pin for hardware write protection control. If you tie this pin to
V
CC,
the write function is disabled to protect previously written data
in the entire memory; if you tie it to V
SS
, the write function is
enabled. This pin is internally pulled down to V
SS.
Single power supply.
Description
Circuit
Type
–
–
3
SCL
WP
Input
Input
2
1
V
CC
–
–
NOTE:
See the following page for diagrams of pin circuit types 1, 2, and 3.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 3 of 22
Rev 1.0 Aug.5, 2002
Fax:886-3-3521052
24LLC16
16K-Bit-Serial EEPROM
WP
SCL
Noise
Filter
Figure 5-3. Pin Circuit Type 1
Figure 5-4. Pin Circuit Type 2
SDA
Data Out
V
SS
Noise
Filter
Data In
Figure 5-5. Pin Circuit Type 3
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 4 of 22
Rev 1.0 Aug.5, 2002
Fax:886-3-3521052
24LLC16
16K-Bit-Serial EEPROM
FUNCTION DESCRIPTION
I C-BUS INTERFACE
2
The 24LLC16 supports the I C-bus serial interface data transmission protocol. The two-wire bus consists of a
serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V
CC
by a
pull-up resistor that is located somewhere on the bus.
2
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions,
2
controlling bus access. Only one 24LLC16 devices can be connected to the I C-bus as slaves (see Figure 5-
6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines
which bus operating mode would be active.
V
CC
R
V
CC
R
SDA
SCL
Master
Bus Master
(Transmitter/
Receiver)
Slave
24LLC16
Figure 5-6. Typical Configuration
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Email: server@ceramate.com.tw
Tel:886-3-3214525
Http: www.ceramate.com.tw
Page 5 of 22
Rev 1.0 Aug.5, 2002
Fax:886-3-3521052
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