LH5481
LH5491
FEATURES
•
Fastest 64
×
8/9 Cascadable FIFO
35/25/15 MHz
•
Expandable in Word Width and
FIFO Depth
•
Almost-Full/Almost-Empty and
Half-Full Flags
•
Fully Independent Asynchronous
Inputs and Outputs
•
LH5481 Output Enable forces Data
Outputs to High-Impedance State
•
Pin-Compatible Replacements for Cypress
CY7C408A/09A or Logic Devices
L8C408/09 FIFOs
•
Industry Standard Pinout
•
Packages:
28-Pin, 300-mil DIP
28-Pin PLCC
FUNCTIONAL DESCRIPTION
The LH5481 and LH5491 are high-performance, asyn-
chronous First-In, First-Out (FIFO) memories organized
64 words deep by eight or nine bits wide. The eight-bit
LH5481 has an Output Enable (OE) function, which can
be used to force the eight data outputs (DO) to a high-im-
pedance state. The LH5491 has nine data outputs.
These FIFOs accept eight or nine-bit data at the Data
Inputs (DI). A Shift In (SI) signal writes the DI data into the
FIFO. A Shift Out (SO) signal shifts stored data to the Data
Outputs (DO). The Output Ready (OR) signal indicates
when valid data is present on the DO outputs.
If the FIFO is full and unable to accept more DI data,
Input Ready (IR) will not return HIGH, and SI pulses will
be ignored. If the FIFO is empty and unable to shift data
to the DO outputs, OR will not return HIGH, and SO
pulses will be ignored. The Almost-Full/Almost-Empty
(AFE) flag is asserted (HIGH) when the FIFO is almost-full
(56 words or more) or almost- empty (eight words or less).
Cascadable 64
×
8 FIFO
Cascadable 64
×
9 FIFO
The Half-Full (HF) flag is asserted (HIGH) when the FIFO
contains 32 words or more.
Reading and writing operations may be asynchronous,
allowing these FIFOs to be used as buffers between
digital machines of different operating frequencies. The
high speed makes these FIFOs ideal for high perform-
ance communication and controller applications.
PIN CONNECTIONS
28-PIN PDIP
AFE
HF
IR
SI
DI
0
DI
1
V
SS
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
NC/DI
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
MR
SO
OR
DO
0
DO
1
V
SS
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
OE/DO
8
5481-1D
TOP VIEW
Figure 1. Pin Connections for DIP Package
28-PIN PLCC
AFE
V
CC
MR
HF
IR
SO
SI
TOP VIEW
4
DI
0
DI
1
V
SS
DI
2
DI
3
DI
4
DI
5
5
6
7
8
9
10
11
3
2
1
28 27 26
25
24
23
22
21
20
19
OR
DO
0
DO
1
V
SS
DO
2
DO
3
DO
4
12 13 14 15 16 17 18
NC/DI
8
DO
6
DI
6
DI
7
OE/DO
8
DO
7
DO
5
5481-2D
Figure 2. Pin Connections for PLCC Package
1
LH5481/91
64
×
8 / 64
×
9 FIFO
ALMOST-FULL/
ALMOST-EMPTY
SI
IR
INPUT
CONTROL
LOGIC
WRITE POINTER
WRITE MULTIPLEXER
HALF-FULL
AFE
HF
.
.
.
DATA OUT
.
.
.
DO
0
DO
7
DO
8
(LH5491)
(LH5491) DI
0
- DI
8
(LH5481) DI
0
- DI
7
DATA IN
MEMORY ARRAY
READ MULTIPLEXER
MR
MASTER
RESET
READ POINTER
OUTPUT
CONTROL
LOGIC
OE
(LH5481)
OR
SO
5481-3
Figure 3. LH5481/91 Block Diagram
PIN DESCRIPTIONS
PIN
PIN TYPE *
DESCRIPTION
PIN
PIN TYPE *
DESCRIPTION
DI
0
– DI
7
DO
0
– DO
7
DI
0
– DI
8
DO
0
– DO
8
SI
SO
IR
OR
I
O/Z
I
O
I
I
O
O
Data Inputs, LH5481
Data Outputs, LH5481
Data Inputs, LH5491
Data Outputs, LH5491
Shift In
Shift Out
Input Ready
Output Ready
HF
AFE
MR
OE
V
CC
V
SS
O
O
I
I
V
V
Half-Full Flag
Almost-Full / Almost-
Empty
Master Reset
Output Enable
(LH5481 only)
Positive Power Supply
Ground
* I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
2
64
×
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×
9 FIFO
LH5481/91
ABSOLUTE MAXIMUM RATINGS
1,2
PARAMETER
RATING
Vcc Range
Input Voltage Range
DC Output Current
3
Storage Temperature
DC Voltage Applied To Outputs In High-Z state
Static Discharge Voltage
4
Power Dissipation (Package Limit)
–0.5 V to 7 V
–0.5 V to Vcc + 0.5 V (not to exceed 7 V)
±40
mA
–65
o
C to 150
o
C
–0.5 V to Vcc + 0.5 V (not to exceed 7 V)
> 2000 V
1.0 W
NOTES:
1. All voltages are measured with respect to Vss.
2. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device.
This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions
above those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
4. Sample tested only.
OPERATING RANGE
PARAMETER
1
MIN
MAX
UNIT
o
C
DESCRIPTION
T
A
V
CC
Vss
V
IL
V
IH
Temperature, Ambient
Supply Voltage
Ground
Input Low Voltage (Logic ‘0’)
2
Input High Voltage (Logic ‘1’)
0.0
4.5
0.0
– 0.5
2.0
70
5.5
0.0
0.8
Vcc + 0.5
V
V
V
V
NOTES:
1. All voltages are measured with respect to Vss.
2. FIFO inputs are able to withstand a –1.5 V undershoot for less than 10 ns per cycle.
DC ELECTRICAL CHARACTERISTICS
1
(Over Operating Range Unless Otherwise Noted)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
MAX
UNIT
I
LI
I
LO
V
OH
V
OL
I
CCQ
I
CC
Input Leakage Current
Output Leakage Current (High-Z)
Output High Voltage
Output Low Voltage
Power Supply Quiescent Current
Power Supply Current
2
V
CC
= 5.5 V, V
IN
= 0 V to V
CC
V
CC
= 5.5 V, V
OUT
= 0 V to V
CC
V
CC
= 4.5 V, I
OH
= –4 mA
V
CC
= 4.5 V, I
OL
= 8.0 mA
V
CC
= 5.5 V, I
OUT
= 0 mA
V
IN
≤
V
IL,
V
IN
≥
V
IH
fsi = 35 MHz, fso = 35 MHz
–10
–10
2.4
10
10
µA
µA
V
0.4
25
45
V
mA
mA
NOTES:
1. All voltages are measured with respect to Vss.
2. Icc is dependent upon actual output loading and cycle rates. Specified values are with outputs open.
3
LH5481/91
64
×
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×
9 FIFO
AC TEST CONDITIONS
1
PARAMETER
RATING
Input Pulse Levels
Input Rise and Fall Times (10% / 90%)
Input Timing Reference Levels
Output Timing Reference Levels
Output Load for AC Timing Tests
NOTE:
1. All voltages are measured with respect to Vss.
0 to 3 V
Figure 4a
1.5 V
1.5 V
Figure 4b
CAPACITANCE
PARAMETER
1,2
DESCRIPTION
TEST CONDITIONS
RATING
C
IN
C
OUT
Input Capacitance
Output Capacitance
T
A
= 25°C, f = 1 MHz, V
CC
= 4.5 V
T
A
= 25
o
C, f = 1 MHz, Vcc = 4.5 V
5 pF
7 pF
NOTES:
1. All voltages are measured with respect to Vss.
2. Sample tested only.
3.0 V
10%
90%
90%
10%
DEVICE
UNDER
TEST
167
Ω
1.73 V
CL = 30 pF *
GND
5 ns
5 ns
5481-18
* INCLUDES JIG AND SCOPE CAPACITANCES
5481-4
Figure 4a. Input Rise and Fall Times
Figure 4b. Output Load Circuit
4
64
×
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×
9 FIFO
LH5481/91
AC ELECTRICAL CHARACTERISTICS
1
(Over Operating Range)
SYMBOL
PARAMETER
15MHz
MIN
MAX
25MHz
MIN
MAX
35MHz
MIN
MAX
UNITS
f
O
t
PHSI
t
PLSI
t
SSI
t
HSI
t
DLIR
t
DHIR
t
PHSO
t
PLSO
t
DLOR
t
DHOR
t
SOR
t
HSO
t
FT
t
BT
t
SIR
t
HIR
t
PIR
t
POR
t
DLZOE
t
DHZOE
t
DHHF
t
DLHF
t
DLAFE
t
DHAFE
t
PMR
t
DSI
t
DOR
t
DIR
t
LXMR
t
AFE
t
HF
t
OD
Operating Frequency
2
SI HIGH Time
3,8
SI LOW Time
3,8
Data Setup to SI
4
Data Hold from SI
4
Delay, SI HIGH to IR LOW
Delay, SI LOW to IR HIGH
SO HIGH Time
3
SO LOW Time
3
Delay, SO HIGH to OR LOW
Delay, SO LOW to OR HIGH
Data Setup to OR HIGH
Data Hold from SO LOW
Fallthrough Time
Bubblethrough Time
Data Setup to IR
5
Data Hold from IR
5
Input Ready Pulse HIGH
8
Output Ready Pulse HIGH
8
OE LOW to LOW Z (LH5481)
6,9
OE HIGH to HIGH Z (LH5481)
6,9
SI LOW to HF HIGH
SO LOW to HF LOW
SO or SI LOW to AFE LOW
SO or SI LOW to AFE HIGH
MR Pulse Width
MR HIGH to SI HIGH
MR LOW to OR LOW
7
MR LOW to IR HIGH
7
MR LOW to Output LOW
7
MR LOW to AFE HIGH
MR LOW to HF LOW
SO LOW to Next Data Out Valid
35
5
5
7
7
–1
0
15
20
15
20
–1
14
15
11
18
–1
12
20
24
11
18
20
24
–1
0
36
28
5
5
7
7
35
35
40
40
40
40
35
25
25
25
25
30
30
26
25
9
17
–1
10
18
20
9
17
18
20
–1
0
34
26
5
5
7
7
30
30
40
40
40
40
35
25
25
25
25
30
30
22
35
MHz
ns
ns
ns
ns
16
18
ns
ns
ns
ns
16
18
ns
ns
ns
ns
30
25
ns
ns
ns
ns
ns
ns
25
25
36
36
36
36
ns
ns
ns
ns
ns
ns
ns
22
20
20
20
30
30
20
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. All time measurements performed at ‘AC Test Conditions.’
2. f
O
= f
SI
= f
SO
.
3. t
PHSI
+ t
PLSI
= t
PHSO
+ t
PLSO
= I/f
O
.
4 t
SSI
and t
HSI
apply when memory is not full.
5. t
SIR
and t
HIR
apply when memory is full and SI is HIGH.
6. High-Z transitions are referenced to the steady-state V
OH
– 500 mV and V
OL
+ 500 mV levels on the output.
7. After reset goes LOW, all Data outputs will be at LOW level, IR goes HIGH and OR goes LOW.
8. Common dash number devices are guaranteed by design to function properly in a cascaded configuration.
5
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