LH5P1632
FEATURES
•
32,768
×
16 bit organization
•
Access time: 80/150 ns (MAX.)
•
Cycle time: 140/210 ns (MIN.)
•
Single +5 V power supply
•
Power consumption (MAX.):
Operating: 467.5/327.5 mW
Standby: 16.5 mW
•
TTL compatible I/O
•
256 refresh cycles/4 ms (MAX.)
•
Available for auto-refresh mode
•
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
DESCRIPTION
CMOS 512K (32K
×
16) Pseudo-Static RAM
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
GND
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
UWR
LWR
A
10
A
11
A
12
A
13
A
14
UOE/TEST
1
LOE/RFSH
CE
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
V
CC
5P1632-1
TOP VIEW
The LH5P1632 is a 512K-bit Pseudo-Static RAM
organized as 32,768
×
16 bits. It is fabricated using
silicon-gate CMOS process technology.
Figure 1. Pin Connections for DIP and
SOP Packages
1
LH5P1632
CMOS 512K (32K
×
16) Pseudo-Static RAM
21 V
CC
20 GND
A
0
11
A
1
10
A
2
9
A
3
8
A
4
7
A
5
6
A
6
A
7
A
8
A
9
5
4
3
2
A
0
- A
7
ROW
ADDRESS
BUFFER
SENSE
AMPS
I/O
SELECTOR
DATA
IN
BUFFER
12 I/O
1
13
14
15
16
I/O
2
I/O
3
I/O
4
V
BB
GENERATOR
40 V
CC
1 GND
A
8
- A
14
COLUMN
ADDRESS
BUFFER
COLUMN
DECODER
A
10
37
A
11
36
A
12
35
A
13
34
A
14
33
REFRESH
ADDRESS
COUNTER
EXT/INT
ADDRESS
MUX
ROW
DECODER
MEMORY
ARRAY
DATA
OUT
BUFFER
I/O
5
17 I/O
6
18 I/O
7
19 I/O
8
DATA
IN
BUFFER
CE 30
CLOCK
GENERATOR
22 I/O
9
23 I/O
10
24 I/O
11
25 I/O
12
26 I/O
13
27 I/O
14
28 I/O
15
29 I/O
16
DATA
OUT
BUFFER
REFRESH
CONTROLLER
LOE/ 31
RFSH
UOE/
TEST
1
32
LWR 38
LWR 39
5P1632-2
Figure 2. LH5P1632 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
– A
14
LWR, UWR
LOE/RFSH, UOE
CE
Address input
Write enable
Output enable/Refresh input
Chip enable input
I/O
1
– I/O
16
V
CC
GND
Data input/output
Power Supply
Ground
2
CMOS 512K (32K
×
16) Pseudo-Static RAM
LH5P1632
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Applied voltage on all pins
Output short circuit current
Power dissipation
Operating temperature
Storage temperature
V
T
I
O
P
D
Topr
Tstg
–1.0 to +7.0
50
600
0 to +70
–65 to +150
V
mA
mW
°C
°C
1
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply voltage
Input voltage
V
CC
GND
V
IH
V
IL
4.5
0
2.4
–0.3
5.0
0
5.5
0
V
CC
+ 0.3
0.8
V
V
V
V
1
NOTE:
1. V
IL
(MIN.) = –1.0 V when the pulse width is less than 20 ns.
CAPACITANCE (T
A
= 0 to +70°C, f = 1 MHz, V
CC
= 5.0 V
±10%)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
A
0
– A
14
Input capacitance
LWR, UWR
CE
LOE/RFSH, UOE
Input/Output capacitance
I/O
1
– I/O
16
C
IN1
C
IN2
C
IN3
C
IN4
C
OUT1
8
5
5
5
10
pF
pF
pF
pF
pF
DC CHARACTERISTICS (T
A
= 0 to +70°C, V
CC
= 5.0 V
±10%)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Average supply current in
normal operation
t
RC
= t
RC
(MIN)
Supply current in
standby mode
Average supply current in
CPU internal cycle
(LWR = UWR = LOE/RFSH =
UOE = V
IH
)
Input leakage current
I/O leakage current
Output HIGH voltage
Output LOW voltage
NOTES:
1. Specified values are with outputs open.
2. I
CC1
and I
CC3
depend on the cycle time.
3. CE = High, LOE/RFSH = High.
LH5P1632-80
I
CC1
I
CC2
LH5P1632-80
I
CC3
LH5P1632-15
0 V
≤
V
IN
≤
6.5 V,
0 V except on test pins
0 V
≤
V
OUT
≤
V
CC
+ 0.3 V,
Outputs in high-impedance
state
I
OUT
= –1.0 mA
I
OUT
= 4.0 mA
–10
–10
2.4
LH5P1632-15
85
mA
65
3.0
85
mA
1, 2
mA
1, 3
1, 2
I
LI
I
LO
V
OH
V
OL
10
10
µA
µA
V
0.4
V
3
LH5P1632
CMOS 512K (32K
×
16) Pseudo-Static RAM
AC CHARACTERISTICS
1, 2, 3
(T
A
= 0 to +70°C, V
CC
= 5.0 V
±10%)
PARAMETER
SYMBOL
MIN.
–80 ns
MAX.
–150 ns
MIN.
MAX.
UNIT
NOTE
READ OR WRITE CYCLE
Random read, write cycle time
Read modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
OE setup time for WR
Output disable time from CE
Output disable time from OE
Output disable time from WR
OE setup time
OE hold time
OE lead time
Write command pulse width
Write command setup time
Write command hold time
Data setup time from WR
Data setup time from CE
Data hold time from WR
Data hold time from CE
Transition time (rise and fall)
Refresh time interval
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto Refresh)
Refresh precharge time (Auto
Refresh)
CE delay time from Refresh active
(Auto Refresh)
t
RC
t
RMW
t
CE
t
P
t
AS
t
AH
t
RCS
t
RCH
t
CEA
t
OEA
t
CLZ
t
OLZ
t
OSW
t
CHZ
t
OHZ
t
WHZ
t
OES
t
OEH
t
OEL
t
WCP
t
WCS
t
WCH
t
DSW
t
DSC
t
DHW
t
DHC
t
T
t
REF
t
FC
t
RFD
t
FAP
t
FP
t
FCE
REFRESH CYCLE
140
50
30
40
160
8,000
10
0
0
0
0
0
10
0
10
60
60
60
30
30
0
0
3
35
4
190
60
80
30
225
8,000
25
25
25
140
205
80
50
0
20
0
0
80
30
10
0
0
0
0
0
10
0
10
85
85
85
50
50
0
0
3
35
4
35
35
35
10,000
210
280
150
60
0
30
0
0
150
70
10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
5
5
4
4
NOTES:
1. In order to initialize the circuit, CE and OEL/RFSH should be kept
V
IH
for 200
µs
after power on and followed by at least 8 dummy
cycles.
2. AC characteristics shall be tested with t
T
= 5 ns.
3. AC characteristics are measured at the following condition (see figure
at right).
4. Address is latched at the negative edge of CE.
5. Measured with a load equivalent to 2TTL + 100 pF.
6. Data for the lower byte (I/O
1
to I/O
8
) is latched at the positive edge
of LWR or the positive edge of CE. Data for the upper byte (I/O
9
to
I/O
16
) is latched at the positive edge of UWR or the positive edge
of CE.
INPUT
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
OUTPUT
5P1632-9
Figure 3. AC Characteristics
4
CMOS 512K (32K
×
16) Pseudo-Static RAM
LH5P1632
TRUTH TABLE
INPUT
CE
UOE
LOE/RFSH
UWR
LWR
OUTPUT
I/O
9
– I/O
16
I/O
1
– I/O
8
MODE
UPPER BYTE
LOWER BYTE
NOTE
H
L
L
L
L
L
L
L
L
L
H
D
L
H
L
H
D
D
H
D
L
D
D
L
L
H
H
D
H
D
L
D
D
H
H
H
H
L
L
H
L
H
D
D
H
H
H
H
L
H
L
H
L
D
High-Z
D
OUT
High-Z
D
OUT
High-Z
D
IN
D
IN
High-Z
D
IN
D
OUT
High-Z
High-Z
D
OUT
D
OUT
High-Z
High-Z
D
IN
High-Z
D
IN
D
OUT
D
IN
High-Z
Read
Standby
Read
Read
CE only refresh
CE only refresh
Write
CE only refresh
Write
Read
Write
Auto Refresh
Inhibit
Inhibit
CE only refresh
Read
CE only refresh
Write
Write
CE only refresh
Write
Read
NOTES:
D = Don’t care.
High-Z = High impedance.
t
RC
t
P
V
IH
V
IL
t
AS
V
IH
V
IL
t
AH
t
CE
t
P
CE
A
0
- A
14
ADDRESS
INPUT
t
OEH
t
OEL
t
OES
LOE/RFSH V
IH
V
IL
UOE
t
RCS
LWR V
IH
UWR V
IL
t
CEA
t
OEA
V
I/O
1
- I/O
16
V
OH
OL
t
OLZ
t
CLZ
5P1632-3
t
RCH
t
CHZ
t
OHZ
VALID-DATA
OUTPUT
Figure 4. Read Cycle
5
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