LH5P8129
FEATURES
•
131,072
×
8 bit organization
•
Access times (MAX.): 60/80/100 ns
•
Cycle times (MIN.): 100/130/160 ns
•
Single +5 V power supply
•
Pin compatible with 1M standard SRAM
•
Power consumption:
Operating: 572/385/275 mW (MAX.)
Standby (TTL level): 5.5 mW (MAX.)
Standby (CMOS level): 1.1 mW (MAX.)
•
TTL compatible I/O
•
Available for auto-refresh and self-refresh
modes
•
512 refresh cycles/8 ms
•
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8
×
20 mm
2
TSOP (Type I)
DESCRIPTION
The LH5P8129 is a 1M bit Pseudo-Static RAM
organized as 131,072
×
8 bits. It is fabricated using
silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo static operation which elimi-
nates external clock inputs, while considering the pinout
compatibility with industry standard SRAMs. The
advantage is the cost savings realized with the lower
cost PSRAM.
The LH5P8129 PSRAM has a built-in oscillator, which
makes it easy to refresh memories without external
clocks.
CMOS 1M (128K
×
8)
CS-Control Pseudo-Static RAM
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
RFSH
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CS
R/W
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
5P8129-1
TOP VIEW
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type I)
TOP VIEW
A
11
A
9
A
8
A
13
R/W
CS
A
15
V
CC
RFSH
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
NOTE:
Reverse bend available on request.
5P8129-2
Figure 2. Pin Connections for TSOP Package
1
LH5P8129
CMOS 1M (128K
×
8) Pseudo-Static RAM
16 GND
32 V
CC
A
0
12
A
1
11
A
2
10
A
3
9
A
4
8
A
5
7
A
6
A
7
A
8
A
9
6
5
27
26
ROW
ADDRESS
BUFFER
EXT/INT
ADDRESS
MUX
ROW
DECODER
SENSE
AMPS
I/O
SELECTOR
DATA
IN
BUFFER
13 I/O
0
14 I/O
1
15 I/O
2
17 I/O
3
MEMORY
ARRAY
DATA
OUT
BUFFER
18 I/O
4
19 I/O
5
20 I/O
6
21 I/O
7
V
BB
GENERATOR
COLUMN
ADDRESS
BUFFER
COLUMN
DECODER
A
10
23
A
11
25
A
12
4
A
13
28
A
14
3
A
15
31
A
16
2
REFRESH
ADDRESS
COUNTER
CE 22
CS 30
CLOCK
GENERATOR
REFRESH
CONTROLLER
RFSH 1
OE 24
R/W 29
REFRESH
TIMER
NOTE:
Pin numbers apply to 32-pin DIP or SOP.
5P8129-3
Figure 3. LH5P8129 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
- A
16
R/W
OE
CE
Address input
Read/Write input
Output Enable input
Chip Enable input
CS
RFSH
I/O
0
- I/O
7
Chip Select input
Refresh input
Data input/output
2
CMOS 1M (128K
×
8) Pseudo-Static RAM
LH5P8129
TRUTH TABLE
CE
CS
OE
R/W
RFSH
A
0
- A
16
I/O
1
- I/O
8
MODE
L
L
L
L
H
H
H
H
H
L
X
X
L
X
H
X
X
X
H
L
H
X
X
X
X
X
X
X
L
H
VX
VX
VY
X
X
X
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
Read
Write
CE only refresh
CS standby
Auto/Self refresh
Standby
NOTES:
H = High at V
IN
= V
CC
+ 0.3 V to V
IH
(MIN.)
L = Low at V
IN
= V
IL
(MAX.) to -1.0 V
X = Don’t care at V
CC
+ 0.3 V to -1.0 V
VX = A
0
-A
16
address input when CE = L, then Don’t Care
VY = A
0
-A
8
address input when CE = L, then Don’t Care,
and A
9
-A
16
address = Don’t Care at V
CC
+ 0.3 V to -1.0 V
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Applied voltage on any pins
Output short circuit current
Power dissipation
Operating temperature
Storage temperature
V
T
I
O
P
D
Topr
Tstg
-1.0 to +7.0
50
600
0 to +70
-65 to +150
V
mA
mW
°C
°C
1
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDI-
TIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
Input voltage
V
CC
GND
V
IH
V
IL
4.5
0
2.4
-1.0
5.0
0
5.5
0
V
CC
+ 0.3
0.8
V
V
V
V
CAPACITANCE (T
A
= 0 to +70°C, f = 1 MHz,
V
CC
= 5.0 V
±10%)
PARAMETER
CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
A
0
- A
16
Input capacitance
R/W, OE
CE, CS
RFSH
Input/output capacitance
I/O
1
- I/O
7
C
IN1
C
IN2
C
IN3
C
IN4
C
OUT1
8
5
5
5
10
pF
pF
pF
pF
pF
3
LH5P8129
CMOS 1M (128K
×
8) Pseudo-Static RAM
DC CHARACTERISTICS (T
A
= 0 to +70°C, V
CC
= 5.0 V
±10%)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
LH5P8129-60
Operating current
LH5P8129-80
LH5P8129-10
Standby current
Self-refresh
average current
Input leakage current
I/O leakage current
Output HIGH voltage
Output LOW voltage
NOTES:
1. Specified values are with outputs open.
2. I
CC1
depends on the cycle time
3. CE = V
IH
, RFSH = V
IH
4. CE = V
CC
- 0.2 V, RFSH = V
CC
- 0.2 V
5. CE = V
IH
, RFSH = V
IL
6. CE = V
CC
- 0.2 V, RFSH = 0.2 V
I
CC1
t
RC
= t
RC
(MIN.)
104
70
50
1
0.2
1
0.2
mA
1, 2
1, 3
1, 4
1, 5
1, 6
TTL Input
CMOS Input
TTL Input
CMOS Input
I
CC2
I
CC3
I
LI
I
LO
V
OH
V
OL
0 V
≤
V
IN
≤
6.5 V
0 V except on test pins
0 V
≤
V
OUT
≤
V
CC
+ 0.3 V
Output in high-impedance state
I
OUT
= -1 mA
I
OUT
= 4 mA
-10
-10
2.4
mA
mA
µA
µA
V
10
10
0.4
V
4
CMOS 1M (128K
×
8) Pseudo-Static RAM
LH5P8129
AC ELECTRICAL CHARACTERISTICS
1,2,3
(T
A
= 0 to +70°C, V
CC
= 5.0 V
±10%)
PARAMETER
SYMBOL
LH5P8129-60
MIN.
MAX.
LH5P8129-80
MIN.
MAX.
LH5P8129-10
MIN.
MAX.
UNIT
NOTE
Random read, write cycle time
Read modify write cycle time
CE pulse width
CE precharge time
CS setup time
CS hold time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Output enable from end of write
Chip disable to output in High-Z
Output disable to output in High-Z
Write enable to output in High-Z
OE setup time
OE hold time
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write
Data setup time from CE
Data hold time from write
Data hold time from CE
Transition time (rise and fall)
Refresh time interval
Refresh command hold time
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width
(Auto refresh)
Refresh precharge time
(Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh
precharge (Self refresh)
t
RC
t
RMW
t
CE
t
P
t
CSS
t
CSH
t
AS
t
AH
t
RCS
t
RCH
t
CEA
t
OEA
t
CLZ
t
OLZ
t
WLZ
t
CHZ
t
OHZ
t
WHZ
t
OES
t
OEH
t
WP
t
WCS
t
WCH
t
DSW
t
DSC
t
DHW
t
DHC
t
T
t
REF
t
RHC
t
FC
t
RFD
t
FAP
t
FP
t
FAS
t
FRS
100
165
60
40
0
15
0
15
0
0
10,000
130
195
80
40
0
20
0
20
0
0
10,000
160
235
100
50
0
25
0
25
0
0
10,000
60
25
20
0
0
20
20
20
0
10
30
30
40
25
25
0
0
3
15
100
30
30
30
8,000
140
8,000
0
10
30
30
50
30
30
0
0
3
15
130
40
30
30
8,000
160
20
0
0
80
30
20
0
0
25
25
25
0
10
30
30
60
35
35
0
0
3
15
160
50
8,000
30
30
8,000
190
100
35
30
30
30
35
8
35
8
35
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
4
4
5
5
6
6
6
6
8,000
NOTES:
1. In order to initialize the circuit, an initial pause of 100
µs
with
CE = V
IH
, RFSH = V
IH
after power-up, followed by at least 8
dummy cycles.
2. AC characteristics are measured at t
T
= 5 ns.
3. AC characteristics are measured at the following condition (see
figure at right).
4. Measured with a load equivalent to 2TTL + 100 pF.
5. Address is latched at the negative edge of CE.
6. Data is latched at the positive edge of R/W or at the positive
edge of CE.
INPUT
2.4 V
0.8 V
2.6 V
0.6 V
2.2 V
0.8 V
OUTPUT
5P8129-4
Figure 4. AC Characteristics
5
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