P
RODUCT
S
PECIFICATIONS
®
Integrated Circuits Group
LH28F008SCT-L12
Flash Memory
8M (1M ×8)
(Model No.: LHF08CH3)
Spec No.: EL104164B
Issue Date: May 7, 1999
SHARP
LHF08CH3
l
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express written permission of the company.
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herein, please observe the conditions written herein
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be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein
application areas. When using
in Paragraph (2), even for the
precautions given in Paragraph
in Paragraph (3).
are designed and manufactured
for the following
the products covered herein for the equipment listed
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*Office electronics
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and measuring equipment
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(2) Those contemplating using the products covered herein for the following equipment
which demands hiqh reliabilitv, should first contact a sales representative
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company and then accept responsibility for incorporating
into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
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&ontrol
and safety devices for airplanes, trains, automobiles,
transportation equipment
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*Gas leak detectors and automatic cutoff devices
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mother safety devices and safety equipment,etc.
and
other
(3) Do not use the products covered herein for the following equipment which demands
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equipment
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Please direct all queries regarding
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1
SHARI=
LHF08CH3
1
CONTENTS
PAGE
1.0 INTRODUCTION
1.1 New Features..
1.2 Product Overview
2.0 PRINCIPLES
PAGE
5.0 DESIGN CONSIDERATIONS
.............................
.23
...................................................
....................................................
................................................
...........................
3
3
3
7
5.1 Three-Line Output Control ................................
.23
5.2 RY/BY# and Block Erase, Byte Write and Lock-Bit
23
Configuration Polling.. .........................................
5.3 Power Supply Decoupling.. ................................
23
5.4 V,, Trace on Printed Circuit Boards.. ............... .23
5.5 v,,, v,,, RP# Transitions.. ..............................
5.6 Power-Up/Down Protection.. .............................
5.7 Power Dissipation ..............................................
6.0 ELECTRICAL SPECIFICATIONS.. .....................
6.1 Absolute Maximum Ratings ...............................
6.2 Operating Conditions .........................................
6.2.1 Capacitance .................................................
.24
.24
24
.25
25
25
25
OF OPERATION..
2.1 Data Protection ...................................................
3.0 BUS OPERATION .................................................
3.1 Read ...................................................................
3.2 Output Disable ....................................................
3.3 Standby ...............................................................
3.4 Deep Power-Down ..............................................
3.5 Read Identifier Codes Operation.. .......................
3.6 Write ....................................................................
4.0 COMMAND DEFINITIONS ....................................
4.1 Read Array Command.. .....................................
4.2 Read Identifier Codes Command ......................
4.3 Read Status Register Command.. .....................
4.4 Clear Status Register Command.. .....................
4.5 Block Erase Command.. ....................................
4.6 Byte Write Command ........................................
4.7 Block Erase Suspend Command.. .....................
4.6 Byte Write Suspend Command.. .......................
7
a
a
6
a
8
9
9
9
12
12
12
12
12
13
13
14
6.2.2 AC Input/Output Test Conditions.. ............... .26
27
6.2.3 DC Characteristics ........................................
6.2.4 AC Characteristics - Read-Only Operations .29
6.2.5 AC Characteristics - Write Operations.. ....... .32
6.2.6 Alternative CE#-Controlled Writes.. ............. .35
6.2.7 Reset Operations .........................................
36
6.2.6 Block Erase, Byte Write and Lock-Bit
Configuration Performance ...........................
7.0 ADDITIONAL
INFORMATION
............................
39
.40
.40
..4 1
4.9 Set Block and Master Lock-Bit Commands.. ..... 14
4.10 Clear Block Lock-Bits Command.. ................... 15
7.1 Ordering Information .........................................
8.0 PACKAGE AND PACKING SPECIFICATIONS
Rev. 1.0
SHAi?P
LHF08CH3
2
LH28FOOSSCT-L12
8M-BIT (1 MB x 8)
SmartVoltage
Flash MEMORY
n SmartVoltage
Technology
- 2.7V(Read-Only),
3.3V or 5V Vcc
- 3.3V, 5V or 12V Vpp
n High-Performance
- 120ns(5V*0.5V),
170ns(2.7V-3.6V)
Read Access Time
150ns(3.3V*O.3V),
n
Automated
Byte Write and Block Erase
- Command User Interface
- Status Register
Enhanced Automated Suspend Options
- Byte Write Suspend to Read
- Block Erase Suspend to Byte Write
- Block Erase Suspend to Read
Extended Cycling Capability
- 100,000 Block Erase Cycles
- 1.6 Million Block Erase Cycles/Chip
Write Interface
Packaging
n
n Operating Temperature
- 0°C to +7O”C
I
High-Density
Symmetrically-Blocked
Architecture
- Sixteen 64K-byte Erasable Blocks
Low Power Management
- Deep Power-Down
Mode
- Automatic Power Savings Mode
Decreases Ice in Static Mode
Enhanced Data Protection Features
- Absolute Protection with Vpp=GND
- Flexible Block Locking
- Block Erase/Byte Write Lockout
during Power Transitions
n
n SRAM-Compatible
n
Industry-Standard
- 40-Lead TSOP
ETOXTM* Nonvolatile
I
n
Flash Techno WY
I
W CMOS Process
(P-type silicon substrate)
n
Not designed
hardened
or rated as radiation
SHARP’s LH28F008SCT-L12
Flash memory with SmartVoltage
technology is a high-density, low-cost, nonvolatile,
?ead/write storage solution for a wide range of applications. Its symmetrically-blocked
architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking,
where code is either directly executed out of flash or
downloaded to DRAM, the LH28F008SCT-L12
offers three levels of protection: absolute protection with V,, at
ZND, selective hardware block locking, or flexible software
block locking. These alternatives
give designers
Jltimate control of their code security needs.
The LH28F008SCT-L12
is manufactured
on SHARP’s
0.38um ETOXTM process
technology.
It come in
ndustry-standard
package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA
architecture, the LH28F008SCT-L12
enables quick and easy upgrades for designs demanding the state-of-the-art.
‘ETOX is a trademark
of Intel Corporation.
Rev. 1.3
LHF08CH3
3
1 INTRODUCTION
This
contains
LH28F008SCT-L12
datasheet
specifications.
Section 1 provides a flash memory
overview.
Sections
2, 3, 4, and 5 describe
the
memory organization
and functionality.
Section 6
covers electrical specifications.
LH28F008SCT-L12
Flash
also
includes
memory
documentation
application
notes
and design
tools which
are
referenced in Section 7.
SmartVoltage
technology provides a choice of Voc
and V,, combinations,
as shown in Table 1, to mee
system performance
and power expectations.
2.7\
V,, consumes
approximately
one-fifth the power o
5V Vo,. But, 5V Vco provides the highest reac
performance.
V,, at 3.3V and 5V eliminates the neec
for a separate
12V converter,
while V,,=12\
maximizes block erase and byte write performance
In addition to flexible erase and program voltages
the dedicated V,, pin gives complete data protectior
when V,+V,,,,.
Table 1. Vc, and V,, Voltage Combinations
Offered by SmartVoltage
Technology
Vpp Voltage
Vr.r: Voltage
-
2.7V(‘)
-..
3.3v, 54, l2V
3.3v
5V
5v. 12v
NOTE:
1. Block erase, byte write and lock-bit configuratior
operations with V,o<3.OV are not supported.
Internal
and
VCC
automatically
configures
read and write operations.
VP,
1.1
New Features
The LH28F008SCT-L12
SmartVoltage Flash memory
maintains
backwards-compatibility
with SHARP’s
28F008SA.
Key enhancements
over the 28F008SA
include:
I
*SmartVoltage
*Enhanced
&r-System
Technology
Capabilities
Suspend
Block Locking
detection
Circuitb
the device for optimizec
Both devices
share a compatible
pinout, status
register,
and
software
command
set.
These
similarities
enable a clean upgrade
from the
28F008SA to LH28F008SCT-L12.
When upgrading, it
is important to note the following differences:
*Because of new feature support, the two devices
have different device codes. This allows
for
software optimization.
l
VPPLK
has been lowered from 6.5V to l.5V to
support 3.3V and 5V block erase, byte write, and
lock-bit configuration operations. The V,, voltage
transitions
to GND is recommended
for designs
that switch V,, off during read operation.
technology,
A Command
User Interface (CUI) serves as the
interface between the system processor and interna
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary
for
block erase, byte write, and lock-bit configuration
operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.3s (5V V,,, 12V
VP,) independent of other blocks. Each block can be
independently
erased
100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in byte increments
typically within 6u.s (5V Vcc, 12V Vpp). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.
*To take advantage of SmartVoltage
allow V,, connection to 3.3V or 5V.
1.2 Product
Overview
The LH28F008SCT-L12
is a high-performance
8M-bit
SmartVoltage Flash memory organized as 1 M-byte of
3 bits. The IM-byte of data is arranged in sixteen
SK-byte
blocks
which are individually erasable,
ockable, and unlockable
in-system.
The memory
nap is shown in Figure 3.
Rev. 1.3
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