P
RODUCT
S
PECIFICATIONS
®
Integrated Circuits Group
LH28F160S5NS-L70
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA4)
Spec No.: EL128040
Issue Date: August 22, 2000
SHARP
. -
LHF16KA4
l Handle this document carefully for it contains material protected by international copyright
law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.
l When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
’
aOffice electronics
l instrumentation and measuring equipment
l Machine tools
*Audiovisual equipment
*Home appliance
*Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
*Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
*Mainframe computers
*Traffic control systems
aGas leak detectors and automatic cutoff devices
*Rescue and security equipment
l Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
*Aerospace equipment
l Communications equipment for trunk lines
*Control equipment for the nuclear power industry
aMedical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
l Please direct all queries regarding the products covered herein to a sales representative
of the company.
Rev.1.9
SHAl?P
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LHFlGKA4
1
CONTENTS
PAGE
1 INTRODUCTION ......................................................
1 .l Product Overview ................................................
2 PRINCIPLES OF OPERATION ................................
2.1 Data Protection ...................................................
3 BUS OPERATION.. ..................................................
3.1 Read ...................................................................
3.2 Output Disable ....................................................
3.3
3.4
3.5
3.6
Standby ...............................................................
Deep Power-Down ..............................................
Read identifier Codes Operation.. .......................
Query Operation ..................................................
3
3
6
7
7
7
7
7
7
8
8
8
8
11
11
11
11
12
12
PAGE
5 DESIGN CONSIDERATIONS ................................
.30
5.1 Three-Line Output Control ................................
.30
5.2 STS and Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit Configuration
Polling.. .............................................................
.30
5.3 Power Supply Decoupling.. ...............................
.30
5.4 V,, Trace on Printed Circuit Boards.. ............... .30
5.5 V,,, V,,, RP# Transitions.. ..............................
.31
5.6 Power-Up/Down Protection.. ............................. .31
5.7 Power Dissipation .............................................
.31
6 ELECTRICAL SPECIFICATIONS.. ........................
6.1 Absolute Maximum Ratings ..............................
6.2 Operating Conditions ........................................
6.2.1 Capacitance ................................................
.32
.32
.32
3.7 Write.. ..................................................................
4 COMMAND DEFINITIONS .......................................
4.1 Read Array Command.. .....................................
4.2 Read Identifier Codes Command.. ....................
4.3 Read Status Register Command.. .....................
4.4 Clear Status Register Command.. .....................
4.5 Query Command ...............................................
4.5.1 Block Status Register ..................................
.32
6.2.2 AC Input/Output Test Conditions.. ............... .33
6.2.3 DC Characteristics.. .....................................
.34
6.2.4 AC Characteristics - Read-Only Operations .36
AC Characteristics - Write Operations.. ....... .39
Alternative CE#-Controlled Writes.. ............. .41
Reset Operations ........................................
.43
Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit
Configuration Performance.. ........................
.44
45
45
6.2.5
6.2.6
6.2.7
6.2.8
4.5.2 CFI Query Identification String.. ................... 13
4.5.3 System Interface Information.. ..................... 13
4.5.4 Device Geometry Definition ......................... 14
4.5.5 SCS OEM Specific Extended Query Table . .
14
4.6 Block Erase Command.. ....................................
15
4.7 Full Chip Erase Command ................................
15
4.8 Word/Byte Write Command.. .............................
4.9 Multi Word/Byte Write Command.. ....................
4.10 Block Erase Suspend Command.. ...................
16
16
17
7 ADDITIONAL INFORMATION ................................
7.1 Ordering Information ..........................................
-
4.11 (Multi) Word/Byte Write Suspend Command ... 17
4.12 Set Block Lock-Bit Command.. ........................ 18
4.13 Clear Block Lock-Bits Command.. ................... 18
4.14 STS Configuration Command ......................... 19
Rev. 1.9
SHAFZP
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LHF16KA4
2
LH28F160S5NSL70
1GM-BIT (2MBx8/1 MBxl6)
Smart 5 Flash MEMORY
I
Smart 5 Technology
- 5V vcc
- sv vpp
n Enhanced Data Protection Features
- Absolute Protection with Vpp=GND
- Flexible Block Locking
- Erase/Write Lockout during Power
Transitions
n Extended Cycling Capability
- 100,000 Block Erase Cycles
- 3.2 Million Block Erase Cycles/Chip
n Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Write and Erase
- Command User Interface
- Status Register
n Industry-Standard Packaging
- 56-Lead SSOP
n ETOXTM’ V Nonvolatile
Technology
Flash
n Common Flash Interface (CFI)
- Universal & Upgradable Interface
n Scalable Command Set (SCS)
n High Speed Write Performance
- 32’Bytes x 2 plane Page Buffer
- 2pslByte Write Transfer Rate
I
I
I
High Speed Read Performance
- 70ns(SV*O.25!/), 80ns(5V*OSV)
Operating Temperature
- 0°C to +7O”C
Enhanced Automated Suspend Options
- Write Suspend to Read
- Block Erase Suspend to Write
- Block Erase Suspend to Read
High-Density Symmetrically-Blocked
Architecture
- Thirty-two 64K-byte Erasable Blocks
Write Interface
x8 or x16 Operation
I
n CMOS Process
(P-type silicon substrate)
n Not designed or rated as radiation
hardened
n SRAM-Compatible
n User-Configurable
SHARP’s LH28F160S5NS-L70
Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
snd extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S5NSL70
offers three levels of protection: absolute protection with V,, at
SND, selective hardware block locking, or flexible software block locking. These alternatives give designers
Jltimate control of their code security needs.
The LH28F160S5NS-L70 is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface
CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer
‘ates and minimize device and system-level implementation costs.
The LH28F160S5NS-L70
is manufactured on SHARP’s 0.35um ETOX TM* V process technology.
ndustry-standard package: the 56-Lead SSOP, ideal for board constrained applications.
‘ETOX is a trademark of Intel Corporation.
Rev. 1.9
It come in
SHARP
.-
1 INTRODUCTION
This
datasheet
contains
LH28F160SSNSL70
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
LHF16KA4
3
execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 70ns (tAvQv) over the commercial
temperature range (0°C to +7O”C) and V,, supply
voltage range of 4.75V-5.25V. At lower V,-c voltage,
the access time is 80ns (4.5V-5.5V).
The Automatic
Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical Icon current is 1 mA at 5V V,,.
When either CEc# or CE,#, and RP# pins are at Vcc,
the ICC CMOS standby mode is enabled. When the
RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(tpHQv) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tPHEL)from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead SSOP (Shrink
Small Outline Package). Pinout is shown in Figure 2.
1.l Product Overview
The LH28F160S5NSL70
is a high-performance 16M-
bit Smart
5 Flash memory
organized
as
2MBx8/1 MBxl6. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 5’ technology provides a choice of Vc, and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 5V Vo,
provides the highest read performance. V,, at 5V
eliminates the need for a separate 12V converter,
while V,,=5V
maximizes
erase
and
write
performance.
In addition to flexible erase and
program voltages, the dedicated V,, pin gives
complete data protection when V+V,,L,.
Table 1. V,, and VP, Voltage Combinations
Offered by Smart 5 Technology
Vcc Voltage
Vpp Voltage
E;v
!iv
detection
Internal
Vco . and
Circuitry
VW
automatically configures the device for optimized
read and write operations.
.I’
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
A block erase operation erases one of the device’s
WK-byte blocks typically within 0.34s (5V Vco, 5V
V,,) independent of other blocks. Each block can be
independently erased 100,000 times (3.2 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
A word/byte write is performed in byte increments
typically within 9.24us (5V Voc, 5V V,,). A multi
word/byte write has high speed write performance of
2uslbyte (5V Voc, 5V V,,). (Multi) Word/byte write
suspend mode enables the system to read data or
Rev. 1.9
单片机
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