IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
N
ONVOLATILE
E
LECTRICALLY
E
RASABLE
PROM
WITH
S
ERIAL
P
ERIPHERAL
I
NTERFACE
(SPI).
DESCRIPTION
The IN25АА020N/D
are a 2K
(256x8)
serial Electrically Erasable PROM with SPI interface.
*
The IN25АА040N/D
are a
4K (512x8)
serial Electrically Erasable PROM with SPI interface (SPI).
The ICs is purposed for reading, writing & nonvolatile data storage in electronic units with SPI interface. ICs
are realized in SO-8 (
MS-012АA) and DIP-8 (MS-001BA)
FEATURES
- Data capacity, Q
INF
:
for IN25АА020N, IN25АА020D
2048 bit,
for IN25АА040N, IN25АА040D
4096 bit;
- Maximum clock frequency, f
C
:
for 4,5 V
≤
U
CC
≤
5,5 V
3 MHz;
for 2,5 V
≤
U
CC
≤
5,5 V
2 MHz;
for 1,8 V
≤
U
CC
≤
5,5 V
1 MHz;
- Maximum stand-by current, I
CC
:
for U
CC
= 5,5 V, U
IL
= 0 V, U
IH
= U
CC
5,0 uA
for U
CC
= 2,5 V, U
IL
= 0 V, U
IH
= U
CC
1,0 uA;
- Maximum read current, I
OCCR
:
for U
CC
= 5,5
В,
f
C
= 3,0
МГц,
SO pin is not loaded .…1,0 mA,
for U
CC
= 2,5
В,
f
C
= 2,0
МГц,
SO pin is not loaded …..0,5 mA;
- Maximum write current, I
OCCW
:
for U
CC
= 5,5 V
5,0 mA;
for U
CC
= 2,5 V
3,0 mA;
- Byte & page (16 bytes) data write modes are available;
- Endurance N
E/W
, …...1000000 cycles;
- Write protection block protect none, 1/4, 1/2, or all of storage
array;
- Power on/off data protection circuitry;
- Supply voltage U
CC
1,8 … 5,5 V;
- Temperature range -40 … +85°C.
- 100 years non-volatile data retention time
N SUFFIX
DIP
8
1
8
1
D SUFFIX
SOIC
PIN FUNCTIONS
Pin
Name
CS
SO
WP
GND
SI
SCK
HOLD
V
CC
Function
Chip Select
Serial Data Output
Write protection
Ground
Serial Data Input
Clock Input
Hold input
*
Power Supply
CS
SO
01
02
08
07
06
05
Vcc
HOLD
SCK
SI
WP
03
GND
04
1
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IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
Block Diagram
Status
counter
HV-generator
Control
logic
Decoder X
I/O
Memory
control logic
EEPROM Array
Page latches
SI
SO
Decoder Y
CS
SCK
HOLD
WP
U
CC
GND
Recommended Operation Conditions & Maximum Ratings*
Parameter, unit
Symbol
Recommended
Operation Conditions
Min
Max
Maximum Ratings
Min
Max
Sense amplifier,
Read/Write control
Supply voltage,V
High level input
voltage, V
Low level input
voltage, V
2,7 V
≤
Ucc
≤
5,5 V
1,8 V
≤
Ucc < 2,7 V
2,7 V
≤
Ucc
≤
5,5 V
1,8 V
≤
Ucc < 2,7 V
Ambient temperature
Ucc
U
IH
U
IL
T
A
1,8
2,0
0,7Ucc
5,5
Ucc + 1,0
Ucc + 1,0
-0,6
–
7,0
Ucc + 1,0
-0,3
-0,3
-40
0,8
0,3U
CC
85
- 0,6
-60
-
150
ESD protection 2000 V.
Input capacity
С
I
, output capacity
С
О
have to be not more than 7pF for U
CC
= 5,0 V & T
A
=
(25±10)
°С.
2
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IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
Electric Parameters ( -40
o
C
≤
T
A
≤
85
o
C
Parameter, unit
Low level output voltage, V
Symbol
U
OL
Mode
2,5 V
≤
U
CC
≤
5,5 V
I
OL
= 2,1 mA
1,8 V
≤
U
CC
≤
2,5 V
I
OL
= 1,0 mA
U
CC
= 1,8 V
I
OH
= -400 uA
U
CC
= 5,5 V
I
OH
= -400 uA
U
I
= 0 V
U
I
= 5,5V
U
I
= 0 V
U
I
= 5,5V
Ucc = 5,5 V, U
IL
= 0 V
U
IH
= Ucc
Ucc = 2,5 V, U
IL
= 0 V
U
IH
= Ucc
Ucc = 5,5 V, f
C
= 3 MHz
SO pin is not loaded
Ucc = 2,5 V, f
C
= 2 MHz
SO pin is not loaded
Ucc = 5,5 V, f
C
= 3 MHz
Ucc = 2,5 V, f
C
= 2 MHz
Min
–
Max
0,4
T
A
,
°С
25 ± 10;
-45; 85
-
1,3
5,0
–
0,2
–
–
High level output voltage, V
U
OH
Low level input leakage current, uA
High level input leakage current, uA
Low level output leakage current,
uA
High level output leakage current,
uA
Consumption current, uA
I
ILL
I
ILH
I
OLL
I
OLH
I
CC
-
-
–
–
–
–
-10,0
10,0
-10,0
10,0
5,0
1,0
1,0
0,5
5,0
3,0
Consumption current (Operating
Read), uA
I
OCC R
Consumption current (Operating
Write), uA
I
OCC W
–
Data access time on SCK tran-
t
V
sition to low level, ns
Output disable time on
CS
high, ns
t
DIS
Output disable time on
HOLD
low, ns
t
HZ
Output enable time on
HOLD
high, ns
t
HV
Write/Erase cycle, ms
Program/erase cycles
t
CY
N
E/W
4,5 V
≤
U
CC
≤
5,5 V,
f
C
≤
3 MHz
2,5 V
≤
U
CC
<
4,5 V,
f
C
≤
2 MHz
1,8 V
≤
U
CC
<
2,5 V,
f
C
≤
1 MHz
4,5 V
≤
U
CC
≤
5,5 V,
f
C
≤
3 MHz
2,5 V
≤
U
CC
<
4,5 V,
f
C
≤
2 MHz
1,8 V
≤
U
CC
<
2,5 V,
f
C
≤
1 MHz
4,5 V
≤
U
CC
≤
5,5 V,
f
C
≤
3 MHz
2,5 V
≤
U
CC
<
4,5 V,
f
C
≤
2 MHz
1,8 V
≤
U
CC
<
2,5 V,
f
C
≤
1 MHz
4,5 V
≤
U
CC
≤
5,5 V,
f
C
≤
3 MHz
2,5 V
≤
U
CC
<
4,5 V,
f
C
≤
2 MHz
1,8 V
≤
U
CC
<
2,5 V,
f
C
≤
1 MHz
U
CC
= 4,5 V, f
C
= 3 MHz
Ucc = 5,0 V
-
-
-
150
230
475
200
250
500
-
-
-
-
-
-
5
–
Ver.00/11.07.2008
IN25AA020(040)-TSe.doc
1711616
-
-
-
100
150
200
100
150
200
–
1000000
25±10
–40
85
3
IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
SPI parameters (-40 °C
≤
Ta
≤
85 °C)
Sym
bol
f
C
t
CSS
t
CSH
t
SU
t
HD
t
CSD
t
R
t
F
t
HI
t
LO
t
CLD
t
CLE
t
HO
t
HS
t
HH
Parameter, unit
Clock frequency,
MHz
CS setup time, ns
CS hold time, ns
SI setup time, ns
SI hold time, ns
Disable time on
CS
,
ns
SCK rise time, us
SCK fall time, us
SCK high time, ns
SCK low time, ns
Clock delay, ns
Clock setup time, ns
Data hold time, ns
475
475
-
-
Mode
C
L
=
100 pF
1,8 V
≤
U
CC
<
2,5 V
Min
-
500
475
50
100
Max
1
-
-
-
-
2,5 V
≤
U
CC
<
4,5 V
Min
-
250
250
50
100
Max
2
-
-
-
-
4,5 V
≤
U
CC
≤
5,5 V
Min
-
100
150
30
50
Max
3
-
-
-
-
Not less 500
Not more 2
Not more 2
230
230
-
-
150
150
-
-
Not less 50
Not less 50
Not less 0
200
200
-
-
100
100
-
-
100
100
-
-
HOLD
setup time,
ns
HOLD
hold time, ns
Instruction Set
Instruction Format
Instruction
IN25АА020N,
IN25АА020D
0000 X011
0000 X010
0000 X100
0000 X110
0000 X101
0000 X001
IN25АА040N,
IN25АА040D
0000 A8011
0000 A8010
0000 0100
0000 0110
0000 0101
0000 0001
Description
READ
WRITE
WRDI
WREN
RDSR
WRSR
Notes
Read data from memory array beginning at se-
lected address
Write data to memory array beginning at se-
lected address
Reset the write enable latch (disable write
operations)
Set the write enable latch (enable write opera-
tions)
Read status register
Write status register
1 X – Don’t care (low or high).
2 A8 is the 9
th
address bit necessary to fully address 512 bytes.
4
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IN25АА020N, IN25АА020D, IN25АА040N, IN25АА040D
Data read sequence
CS
0
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16
17 18
19 20 21 22 23
Instruction
SI
0
0
0
0
A8
0
1
1
A7
Lower address byte
6
5
4
3
2
1
A0
Output data
SO
High-Z
7
6
5
4
3
2
1
0
There are six 8-bit instructions available for executing of read/write operation. The feature
of IN25AA040N, IN25AA040D with 4K capacity is that higher address byte (А8) is transmitted by
5
th
bit of data read/write instruction , for IN25AA020N, IN25AA020D with 2K capacity 5
th
bit of
instruction (A8) is ignored.
Enable/disable instructions
а)
“Write enable” - WREN & b) “Write disable” - WRDI
CS
0
1
2
3
4
5
6
7
CS
0
SCK
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
SI
0
0
0
0
0
1
10
0
SO
High-Z
a)
SO
High-Z
b)
The powers up set ICs in the write disable state. For writing operation after power-up or
after an
WRDI
(write disable) instruction,
WREN
(write enable) instruction must be issued.
Any read/write operation can be executed on condition that
CS
=0 (enable signal) , high level on
CS
pin switch IC to standby mode. Already intiated programming cycle will be comleted inde-
pendently from
CS
signal. A low to high transition on
CS
after a valid write sequence initiates an
internal write cycle.
5
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