HI-8591
August 2012
ARINC 429
Line Receiver
PIN CONFIGURATIONS
VCC - 1
TESTA - 2
RINB - 3
RINA - 4
8 - TESTB
7 - ROUTB
6 - ROUTA
5 - GND
DESCRIPTION
The HI-8591 is an ARINC 429 bus interface receiver
designed to operate from a single 3.3 V or 5 V supply. The
part is designed with high-impedance inputs to minimize
bus loading, and has an exceptional input common-mode
performance in excess of +/- 30V, making it immune to
ground offsets around the aircraft. The RINA and RINB
inputs of the standard HI-8591 may be connected directly
to the ARINC 429 bus. To enable external lightning protec-
tion circuitry to be added, the HI-8591-40 variant is avail-
able. The HI-8591-40 requires only the addition of external
40 K
W
, ¼ watt resistors in series with RINA and RINB to
allow the part to meet the lightning protection requirements
of DO-160D level 3.
The typical 10 volt differential ARINC 429 signal is trans-
lated and input to a window comparator and latch. The
comparator levels are set just below the standard 6.5 volt
minimum ARINC data threshold and just above the stan-
dard 2.5 volt maximum ARINC null threshold.
The TESTA and TESTB inputs bypass the analog inputs for
testing purposes. Also if TESTA and TESTB are both taken
high, the digital outputs are forced to zero.
See Holt Application Note AN-300 for more information on
lightning protection.
HI-8591PSI, HI-8591PST & HI-8591PSM
HI-8591PSI-40, HI-8591PST-40 & HI-8591PSM-40
8 - PIN PLASTIC NARROW BODY SOIC
NC
VCC
TESTB
NC
TESTA
RINB
RINA
NC
1
2
3
4
16
15
14
13
12
11
10
9
ROUTB
NC
ROUTA
NC
HI-8591PCI, HI-8591PCT, HI-8591PCI-40 & HI-8591PCT-40
16- pin 4mm x 4mm Chip-scale package
SUPPLY VOLTAGES
vcc
= 3.3V ± 10%, 5.0V ± 10%
FEATURES
!
!
!
!
!
!
!
FUNCTION TABLE
RINA
-1.25V to 1.25V
-3.25V to -6.5V
3.25V to 6.5V
X
X
RINB
-1.25V to 1.25V
3.25V to 6.5V
-3.25V to -6.5V
X
X
X
TESTA
0
0
0
0
1
1
TESTB
0
0
0
1
0
1
ROUTA ROUTB
0
0
1
0
1
0
0
1
0
1
0
0
ARINC 429 line receiver interface in a
small outline package
3.3V single rail supply voltage
+/-30 V common-mode performance
>140 KOhm input impedance
Lightning protection simplified with the
ability to add 40 KOhm external series
resistors
Receiver input hysteresis at least 2 volt
Test inputs bypass analog inputs and
force digital outputs to a one, zero or
null state
X
PIN DESCRIPTION TABLE
SYMBOL
VCC
TESTA
RINB
RINA
GND
ROUTA
ROUTB
TESTB
FUNCTION
SUPPLY
LOGIC INPUT
ARINC INPUT
ARINC INPUT
POWER
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC INPUT
DESCRIPTION
3.3V or 5V SUPPLY
CMOS
RECEIVER B INPUT
RECEIVER A INPUT
GROUND
RECEIVER CMOS OUTPUT A
RECEIVER CMOS OUTPUT B
CMOS
(DS8591, Rev. G)
HOLT INTEGRATED CIRCUITS
www.holtic.com
NC
GND
NC
NC
5
6
7
8
08/12
HI-8591
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 140K
W
of resis-
tance between the ARINC bus and comparator. This resis-
tance is completely on-chip for the HI-8591. In contrast,
the HI-8591-40 has 100 K
W
on-chip and requires an exter-
nal 40K
W
, ¼ watt resistor on each of the ARINC 429 input
pins. The HI-8591-40 device is typically chosen for appli-
cations where lightning protection is a requirement.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider
between VCC and Ground. The nominal settings corre-
spond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, the HI-
8591 outputs are pulled low. This allows the digital out-
puts of a transmitter to be connected to the test inputs
through control logic for system self-test purposes.
ONE
S
R
Q
LATCH
TEST
ROUTA
TESTA
TESTB
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
NULL
TEST
ZERO
S
R
Q
LATCH
ROUTB
TESTA
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
3.3V
1
HARDWIRE
OR
DRIVE FROM LOGIC
{
2
8
4
VCC
TESTA
TESTB
ROUTA
ROUTB
6
7
RXD1
RXD0
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8591 interfacing an ARINC 429 bus input
to a 3.3V ASIC or FPGA. In this example a
HI-8586 ARINC 429 line driver is used to
take 3.3V logic outputs and generate the nec-
essary 10V differential signal for driving an
ARINC 429 bus.
HI-8591
RINA
ARINC
Channel
3
FPGA
5
RINB GND
15V
1
6
ARINC
Channel
SLP1.5
TXAOUT
V+
TX1IN
TX0IN
V-
8
3
2
TXD1
TXD0
7
HI-8586
TXBOUT
GND
4
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8591
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground
Supply voltages
VCC......................................-0.3V to +7V
ARINC input - pins 3 & 4
Voltage at either pin.........+120V to -120V
DC current per input pin.................... ±10mA
Power dissipation at 25°C
plastic DIP............0.7W
ceramic DIP..........0.5W
Solder Temperature
Plastic - leads
Plastic - body
+280°C for 10 sec
+260°C Max.
NOTE: Stresses above absolute maximum
ratings or outside recommended operating con-
ditions may cause permanent damage to the
device. These are stress ratings only. Opera-
tion at the limits is not recommended.
Supply Voltages
VCC..............................3.3V to 5V ± 10%
Temperature Range
Industrial Screening........-40°C to +85°C
Hi-Temp Screening.......-55°C to +125°C
Military Screening.........-55°C to +125°C
RECOMMENDED OPERATING CONDITIONS
Storage Temperature........-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 3.3V ± 10% or 5.0V ± 10% UNLESS OTHERWISE STATED
PARAMETERS
ARINC input voltage
one or zero
null
common mode
logic input voltage
high
low
ARINC input resistance
RINA to RINB
RINA or RINB to GND
RINA or RINB to VCC
logic input current
source
sink
logic output drive voltage
one
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VDIN
VNIN
VCOM
VIH
VIL
R DIFF
R GND
R VCC
IIH
IIL
VOH1
VOH2
Differential volt., pins 3 & 4
"
"
"
with respect to ground
6.5
-
-30.0
10
-
-
13
2.5
+30.0
volts
volts
volts
75% VCC
-
-
-
-
25% VCC
volts
volts
Supplies floating
"
"
"
"
-
-
-
140
140
100
-
-
-
KW
KW
KW
VIN = 2.0V
VIN = 0.8V
VCC = 5V ± 10% IOH = 5mA
VCC= 3.3V ± 10% IOH = 1.5mA
-
-
-
-
20.0
20.0
µA
µA
2.4
2.4
-
-
-
-
-
-
-
-
0.5
0.4
V
V
V
V
zero
VOL1
VOL2
VCC = 5V
± 10% IOH
= 5mA
VCC = 3.3V
± 10% IOH
= 1.5mA
Current drain
operating
ICC1
pins 2, 8 = 0V; pins 3, 4 open
HOLT INTEGRATED CIRCUITS
3
-
1.5
5.0
mA
HI-8591
AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 3.3V ± 10% or 5.0V ± 10% UNLESS OTHERWISE STATED
PARAMETERS
Receiver propagation delay
Output high to low
Output low to high
SYMBOL
TEST CONDITIONS
defined in Figure 3, C L= 50pF
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
defined in Figure 4, C L= 50pF
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
VCC = 3.3V ± 10%
VCC = 5.0V ± 10%
VCC = 3.3V or 5.0V ± 10%
-
-
15
15
50
50
ns
ns
MIN
TYP
MAX
UNITS
t phlr
t plhr
-
-
-
-
600
600
600
600
1000
900
1000
900
ns
ns
ns
ns
TEST pin propagation delay
Output high to low
Output low to high
Receiver output transition times
Output high to low
Output low to high
Input capacitance (1)
ARINC differential
ARINC single ended to Ground
Logic
Notes: 1. Guaranteed but not tested
t pth
t ptl
-
-
-
-
-
-
-
-
100
60
100
60
ns
ns
ns
ns
t fr
t rr
CAD
CAS
C IN
-
-
-
5
-
-
10
10
10
pF
pF
pF
VDIFF
pin 4 - pin 3
t plhr
t phlr
90%
10V
0V
-10V
t rr
VCC
0V
t fr
VCC
0V
pin 6
t plhr
10%
t phlr
pin 7
FIGURE 3 - RECEIVER TIMING
TESTA or B
pin 2 or pin 8
t pth
t ptl
pin 6 or pin 7
FIGURE 4 - TEST PIN TIMING
HOLT INTEGRATED CIRCUITS
4
VCC
0V
VCC
0V
HI-8591
HEAT SINK - CHIP-SCALE PACKAGE ONLY
The HI-8591PCI and HI-8591PCT use a 16-pin plastic
chip-scale (QFN) package. This package has a metal heat
sink pad on its bottom surface. This heat sink should be
soldered down to the printed circuit board for optimum
thermal dissipation. The heat sink is electrically isolated
from the chip and can be soldered to any ground or power
plane. However, since the chip’s substrate is at V+,
connecting the heat sink to this power plane is
recommended to avoid coupling noise into the circuit.
ORDERING INFORMATION
HI - 8591 xx x x - xx
PART
NUMBER
INPUT SERIES RESISTANCE
BUILT-IN
REQUIRED EXTERNALLY
No dash number
-40
PART
NUMBER
140 Kohm
100 Kohm
LEAD
FINISH
0
40 Kohm
Blank
F
PART
NUMBER
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
T
M
PART
NUMBER
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
PACKAGE
DESCRIPTION
I
T
M
NO
NO
YES
PC
PD
PS
CR
16 PIN PLASTIC 4 x 4 mm CHIP SCALE (16PCS) not available with “M” flow
8 PIN PLASTIC DIP (8P) not available with “M” flow
8 PIN PLASTIC NARROW BODY SOIC (8HN)
8 PIN CERDIP (8D) not available Pb-free
HOLT INTEGRATED CIRCUITS
5
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