September 2006
HYB18L256160B[C/F]-7.5
HYE18L256160B[C/F]-7.5
HYE18L256160BCL-7.5
HYE18L256160BFL-7.5
DRAMs for Mobile Applications
256-Mbit Mobile-RAM
D ata Sh eet
Rev. 1.73
Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
HYB18L256160B[C/F]-7.5, HYE18L256160B[C/F]-7.5, HYE18L256160BCL-7.5, HYE18L256160BFL-7.5
Revision History: 2006-09, Rev. 1.73
Page
All
Subjects (major since last revision)
Qimonda update
added disclaimer
53
29
8
12
42
15, 29, 50
Rev. 1.71: deleted -BCX and BFX product types
Table 25:
Updated
Chapter 2.1:
added to note 6: Programming of the Extended Mode Register...
Extended Mode Register table: Editorial changes
Chapter 2.2.1.6:
Editorial change
Chapter 2.4.9.2:
replaced last paragraph by: If during normal operation...
Table 9, Table 13
and
Table 26:
tIH changed
Table 26:
note 7 changed: If tT > 1ns, a value of [0.5 x (tT -1)] ns...
Table 25:
editorial changes
Previous Revision: Rev. 1. 61
Previous Revision: 2005-07, Rev. 1.72
Previous Revision: Rev. 1.6
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01302004-CZ2R-J9SE
2
Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
1
1.1
•
•
•
•
•
•
•
•
•
•
•
•
Overview
Features
4 banks
×
4 Mbit
×
16 organization
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Programmable CAS latency: 2, 3
Programmable burst length: 1, 2, 4, 8 or full page
Programmable wrap sequence: sequential or interleaved
Programmable drive strength
Auto refresh and self refresh modes
8192 refresh cycles / 64 ms
Auto precharge
Commercial (0°C to +70°C) and Extended (-25°C to +85°C) operating temperature range
54-ball P-VFBGA package (12.0
×
8.0
×
1.0 mm)
Power Saving Features
•
•
•
•
•
Low supply voltages:
V
DD
= 1.65V to 1.95V,
V
DDQ
= 1.65V to 1.95V
Optimized self refresh (
I
DD6
) and standby currents (
I
DD2
/
I
DD3
)
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Power-Down and Deep Power Down modes
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Access Time (
t
ACmax
)
Clock Cycle Time (
t
CKmin
)
CL = 3
CL = 2
CL = 3
CL = 2
- 7.5
133
5.4
6.0
7.5
9.5
Unit
MHz
ns
ns
ns
ns
TABLE 2
Memory Addressing Scheme
Item
Banks
Rows
Columns
Addresses
BA0, BA1
A0 - A12
A0 - A8
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
3
Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
TABLE 3
Ordering Information
Type
1)
HYB18L256160B[C/F]
HYB18L256160B[C/F]
Description
Package
Commercial Temperature Range
133 MHz 4 Banks
×
4 Mbit
×
16 LP-SDRAM P-VFBGA-54-2
133 MHz 4 Banks
×
4 Mbit
×
16 LP-SDRAM P-VFBGA-54-2
Extended Temperature Range
HYB18L256160BC-7.5
HYB18L256160BCL-7.5
HYB18L256160BF-7.5
HYB18L256160BFL-7.5
133 MHz 4 Banks
×
4 Mbit
×
16 LP-SDRAM P-VFBGA-54-2
133 MHz 4 Banks
×
4 Mbit
×
16 LP-SDRAM P-VFBGA-54-2
133 MHz 4 Banks
×
4 Mbit
×
16 LP-SDRAM P-VFBGA-54-2
133 MHz 4 Banks
×
4 Mbit
×
16 LP-SDRAM
1) HY[B/E]: Designator for memory products (HYB: Standard temp. range; HYE: extended temp. range)
18L: 1.8 V Mobile-RAM
256: 256 MBit density
160: 16 bit interface width
B: die revision
C / F: lead-containing product (C) / green product (F)
L: low-power product
-7.5: speed grade(s): min. clock cycle time
1.2
Pin Configuration
FIGURE 1
Standard Ballout 256-Mbit Mobile-RAM
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
4
Data Sheet
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
1.3
Description
The HY[B/E]18L256160B[C/F]L is especially designed for
mobile applications. It operates from a 1.8 V power supply.
Power consumption in self refresh mode is drastically
reduced by an On-Chip Temperature Sensor (OCTS); it can
further be reduced by using the programmable Partial Array
Self Refresh (PASR).
A conventional data-retaining Power Down (PD) mode is
available as well as a non-data-retaining Deep Power Down
(DPD) mode.
The HY[B/E]18L256160B[C/F]L is housed in a 54-ball P-
VFBGA package. It is available in Commercial (0
°C
to +70
°C)
and Extended (-25
°C
to +85
°C)
temperature ranges.
The HY[B/E]18L256160B[C/F]L is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The HY[B/E]18L256160B[C/F]L achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to the system clock. Read and write accesses are burst-
oriented; accesses start at a selected location and continue
for a programmed number of locations (1, 2, 4, 8 or full page)
in a programmed sequence.
The device operation is fully synchronous: all inputs are
registered at the positive edge of CLK.
FIGURE 2
Functional Block Diagram
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
5
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