Advance Data
TSC4D272E09 / 18 / 36
72Mb Synchronous Double Transfer Rate (DTRII+™) 3T-iRAM™
With Common I/O, 2.5 Cycle Read Latency
Burst of 2
SRAM-Compatible
Features
Error-resistant 3T-iRAM™ technology
300 to 400 MHz clock for high bandwidth
Read latency of 2.5 clock cycles
DTRII+™ Interface with Common I/O bus
Fully pin-compatible with DDRII+ SRAMs
JEDEC-standard pinout and package
Burst of 2 Read and Write (Byte Writes)
1.8 V core power supply, 1.5 V I/O
Synchronous internally self-timed Writes
ZQ pin for programmable output drive strength
QVLD pin indicates valid output data
DLL for accurate data placement
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump 15mm x 17mm BGA, 1 mm bump pitch
Pin-compatible with 9Mb, 18Mb, 36Mb, and 144Mb
devices
Functional Description
3T-iRAM™ is a unique type of dynamic memory. Tezzaron
has crafted these pseudo-static devices to provide entirely
SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10
times lower than equivalent high-speed, high-density
SRAMs.
DTRII+™ is a double transfer rate interface that is
implemented with Common I/O architecture in these
devices, making them drop-in compatible with DDRII+
SRAMs.
These synchronous pipelined 72Mb 3T-iRAM devices
employ two register clocks, K and
K
. These are
independent single-ended clock inputs, not differential
inputs. All synchronous inputs pass through registers
controlled by the K clocks. Accesses are initiated on the
rising edge of the positive clock and data is registered or
driven on the rising edges of both clocks.
Write (input) and Read (output) data share the same data
pins. Data outputs are tightly matched to two free-running
echo clocks, CQ and
CQ
, which are referenced with
respect to the K clocks. Data inputs are controlled by self-
timed Write circuitry.
These devices always transfer data in two packets. A0 is
internally set to 0 for the first transfer of a data burst and
automatically incremented to 1 for the second transfer.
Options
Configurations:
8M x 9
4M x 18
2M x 36
165 FBGA
400 MHz
375 MHz
333 MHz
300 MHz
Marking
S09
S18
S36
B
-400
-375
-333
-300
Package:
Speed (MHz):
Part number example:
TSC4D272E18B-333
Speed Parameter Synopsis:
(all units ns)
tKHKH
tKHQV
-400
2.50
0.45
-375
2.66
0.45
-333
3.00
0.45
-300
3.30
0.45
Rev. 1.0 – 12 February 2007
Page 1 of 24
©2007, Tezzaron Semiconductor Corp.
Advance Data
TSC4D272E09 / 18 / 36
Pin Configurations
2M x 36: Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
2
NC/144M
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW2
BW3
6
K
7
BW1
BW0
8
LD
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
Doff
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
TDO
Notes:
BW 0
controls writes to DQ0:DQ8;
BW1
controls writes to DQ9:DQ17;
BW 2
controls writes to DQ18:DQ26;
BW 3
controls writes to DQ27:DQ35.
Rev. 1.0 – 12 February 2007
Page 2 of 24
©2007, Tezzaron Semiconductor Corp.
Advance Data
TSC4D272E09 / 18 / 36
4M x 18: Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
2
SA
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
6
K
7
NC
BW0
8
LD
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
Doff
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
TDO
Notes:
BW 0
controls writes to DQ0:DQ8;
BW1
controls writes to DQ9:DQ17
Rev. 1.0 – 12 February 2007
Page 3 of 24
©2007, Tezzaron Semiconductor Corp.
Advance Data
TSC4D272E09 / 18 / 36
8M x 9: Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
2
SA
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
SA
4
R/
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NC
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
7
NC
BW0
8
LD
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
DQ8
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
Doff
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
QVLD
NC
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
TDO
Rev. 1.0 – 12 February 2007
Page 4 of 24
©2007, Tezzaron Semiconductor Corp.
Advance Data
TSC4D272E09 / 18 / 36
Pin Descriptions
Symbol
SA
LD
Type
I
NPUT
I
NPUT
---
I
NPUT
I
NPUT
I
NPUT
I
NPUT
I
NPUT
I
NPUT
O
UTPUT
I
NPUT
I
NPUT
O
UTPUT
I/O
I
NPUT
O
UTPUT
S
UPPLY
S
UPPLY
G
ROUND
--- / I
NPUT
Description
Synchronous address inputs, both Read and Write
Synchronous load; low initiates an access
Not connected to die; can be tied to any voltage
Read/Write select
Byte write controls
Input clocks (positive/negative)
TAP: Test mode select
TAP: Test data input
TAP: Test clock
TAP: Test data output
HSTL input reference voltage
Output impedance matching; connect to Vss through a resistor or else tie to V
DDQ
Valid Output Data indicator
Synchronous data signals for Write and Read
Disable DLL (when low) – affects device mode and timing! See DLL, page 7
Output echo clock (positive/negative)
Power supply to core; 1.8 V nominal
Isolated output buffer supply; 1.5 V nominal
Ground
For address expansion; can be tied to any voltage.
NC
R/
W
BW0
–
BW3
K/
K
TMS
TDI
TCK
TDO
V
REF
ZQ
QVLD
DQ
X
Doff
CQ /
CQ
V
DD
V
DDQ
V
SS
NC/144M
Functional Details
Clocks
K and
K
are the input clocks. All accesses are initiated on rising edges of K; rising edges of both clocks are used to
capture synchronous inputs and to drive out data.
CQ and
CQ
are free-running echo clocks, generated by the RAM, that can be used to simplify data capture in high-speed
systems. These clocks are referenced with respect to the K clocks.
Burst Operations
Read and write operations are synchronous pipelined "burst" operations. Every Read (or Write) command issues (or
accepts) two beats of data in one clock cycle, executing data transfers on subsequent rising clock edges, as illustrated in
the timing diagrams. It is not possible to stop a burst once it starts; two beats of data are always transferred.
Read Cycles
A Read access is initiated by asserting R/
W
high and
LD
low on a rising edge of K and presenting the address to the SA
pins at the same time. The address is stored in the Read address register. After two more rising edges of K, the RAM
produces data out on the DQ pins in response to the next rising edge of
K
. The second beat of data is transferred in
response to the next rising edge of K, for a total of two transfers per address load. Read accesses may be initiated on
every rising edge of K to produce a constant stream of output data timed by the rising edges of K and
K
.
If all pending Read transactions are completed, internal circuitry tri-states the Q pins after the next rising edge of
K
.
Rev. 1.0 – 12 February 2007
Page 5 of 24
©2007, Tezzaron Semiconductor Corp.
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