CD54HCT112 High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger
参数名称 | 属性值 |
Rating | Military |
IOL(Max)(mA) | -6 |
Voltage(Nom)(V) | 5 |
tpd @ nom Voltage(Max)(ns) | 44 |
Package Group | CDIP|16 |
IOH(Max)(mA) | 6 |
ICC @ nom voltage(Max)(mA) | 0.04 |
F @ nom voltage(Max)(Mhz) | 25 |
VCC(Max)(V) | 5.5 |
Technology Family | HCT |
Schmitt trigger | No |
VCC(Min)(V) | 4.5 |
Bits(#) | 2 |
CD54HCT112 | 5962-8970201EA | CD54HC112F3A | CD54HCT112F3A | CD54HC112 | CD74HC112 | CD74HCT112 | |
---|---|---|---|---|---|---|---|
描述 | CD54HCT112 High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger | High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125 | High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125 | High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125 | CD54HC112 High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger | CD74HC112 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | CD74HCT112 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
Rating | Military | - | - | - | Military | Catalog | Catalog |
IOL(Max)(mA) | -6 | - | - | - | -6 | 6 | 6 |
Voltage(Nom)(V) | 5 | - | - | - | 3.3,5 | 3.3,5 | 5 |
tpd @ nom Voltage(Max)(ns) | 44 | - | - | - | 53 | 53 | 44 |
Package Group | CDIP|16 | - | - | - | CDIP|16 | PDIP|16,SOIC|16,SO|16,TSSOP|16 | PDIP|16 |
IOH(Max)(mA) | 6 | - | - | - | 6 | -6 | -6 |
ICC @ nom voltage(Max)(mA) | 0.04 | - | - | - | 0.04 | 0.04 | 0.04 |
F @ nom voltage(Max)(Mhz) | 25 | - | - | - | 70 | 70 | 25 |
VCC(Max)(V) | 5.5 | - | - | - | 6 | 6 | 5.5 |
Technology Family | HCT | - | - | - | HC | HC | HCT |
Schmitt trigger | No | - | - | - | No | No | No |
VCC(Min)(V) | 4.5 | - | - | - | 2 | 2 | 4.5 |
Bits(#) | 2 | - | - | - | 2 | 2 | 2 |
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