2.5 Gbit/s
Clock and Data
Recovery Circuit
GD16504
Preliminary
General Description
The GD16504 is a high performance
monolithic integrated 2.488 Gbit/s
Clock
and Data Recovery
(CDR) device appli-
cable for optical communication systems
including:
u
SDH STM-16
u
SONET OC-48.
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase onto the incoming data.
The electrical input sensitivity is better
than 20 mV. Optical receivers with sensi-
tivity better than -34 dBm have been ob-
tained without optical pre-amplification.
The device meets all ITU-T jitter require-
ments when used with the recommended
loop filter (jitter tolerance, -transfer and
-generation).
The integrated 1:16 demultiplexer with
differential ECL outputs ensures a simple
and universal interface to the system
CMOS ASICs.
The 155 MHz output clock is maintained
within 500 ppm tolerance even in ab-
sence of data.
A triggerable Frame Alignment circuit de-
tecting the occurrence of a framing pat-
tern and aligning data at the 16 bit output
interface. Once the frame is found, the
circuit detects and flags all A1A1A2A2
sequences at the aligned byte boundary.
All high speed I/O levels are ECL com-
patible. The data input has improved
sensitivity and is connected via a 50
Ω
loop through transmission line to mini-
mize stub related reflections.
It is packed in a plastic fpBGA with inter-
nal 50
Ω
transmission lines, heat trans-
port to PCB, reduced mechanical stress
and removed requirement for a heat sink.
All signals are available in two outher
ring for easy routing.
It is also available in a 68 pin leaded
Multi Layer Ceramic (MLC) package with
50
Ω
transmission lines and cavity down
for easy cooling/heat sinking.
Frame Align.
Features
l
Clock and Data Recovery at
2.488 Gbit/s.
SDH STM-16, SONET OC-48 com-
patible.
Differential Data inputs better than
20 mV sensitivity for BER 10
-9
.
Differential ECL Data and Clock
outputs.
Acquisition time < 500
µs.
Few external passive components
needed.
50
Ω
Loop-Through data inputs for
higher sensitivity.
Frame Detection and user triggered
alignment at 16 bits boundary.
Single supply operation.
Power dissipation: 2.5 W
Available in:
– 144 ld. fpBGA
– 68 pin Multi Layer Ceramic leaded
package with 50
Ω
transmission
lines.
GD16504-68BA is 100% interchange-
able with GD16045, only loop filter
has to be changed.
l
l
l
l
l
l
l
l
l
l
FFIN
FFINN
VSOPEN
SOP
SON
FP
FPN
CKOUT
CKOUN
Clock
Divide
LD
LOS
DI
SIPO
SIPI
SINI
SINO
De-
MUX
DOUT0
DOUN0
DOUT15
DOUN15
l
+
-
SELTCK
TCK
DI
SEL1
SEL2
Dec.
Bang
Bang
Phase
Detector
DO
U
D
Applications
l
VCO
4:2
MUX
U
D
VCTL
OUCHP
VDD
VDDA
VEE
VEEA
VCSREF
LOCK
R
Lock
Detect
Circuit
Clock and Data Recovery for:
– SDH STM-16
– SONET OC-48 systems
Data Sheet Rev. 04
V
REFCK
REFCKN
:4
R
Phase
Frequency
Detector
U
Charge
Pump
D
Functional Details
The main application of the GD16504 is
as Clcok and Data Recovery in optical
communication systems including:
u
SDH STM-16
u
SONET OC-48
It integrates:
u
a Voltage Controlled Oscillator (VCO)
u
a Lock Detect Circuit
u
a Frequency Detector (PFD)
u
a 1:16 DeMUX with framer.
u
a Bang-Bang Phase Detector
into a clock and data recovery circuit
followed by a 1:16 demultiplexer with
differential ECL data and clock outputs.
tion occurs between 2 consecutive bits -
the value of the sample in the transition
between the bits determines whether the
VCO clock leads or lags the data. Hence
the
Phase Locked Loop
(PLL) is con-
trolled by the bit transition point, thereby
ensuring that data is sampled in the mid-
dle of the eye, once the system is in CDR
mode. The external loop filter controls
the characteristics of the PLL.
small (few degrees), forcing the loop to
be at one edge of the error-function
shaped transfer characteristic of the
detector.
If a LOS is detected by the optical circuit
in front of GD16504, the SEL1 and SEL2
may be configured to force the PLL to
use the Frequency Detector providing a
stable output clock locked only to refer-
ence input regardless of Lock Detect sta-
tus and at the same time force all outputs
to logic low.
The configuration signals (SEL1 and
SEL2) may be tied to VDD or VEE di-
rectly. The combination resets all Flip
Flops, and sets both Up and Down active
at the input of the Charge Pump, leaving
the output in the middle of its output
range. Since the circuit is self synchro-
nizing, reset need not be asserted during
power up.
OUCHP
330R
82R 100nF
VCO
The VCO is a low noise LC-type differen-
tial oscillator running 2.488 GHz. Tuning
is done by applying a voltage to the
VCTL pin.
VCTL
Figure 1.
Loop Filter
The binary output of either the PFD or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is fed to a charge pump capable of
sinking or sourcing current or tristating.
The output of the charge pump is filtered
through the loop filter and controls the
tuning-voltage of the VCO.
A result of the continuous lock-detect
monitoring circuit is that the VCO fre-
quency never deviates more than
500 ppm (2000 ppm) from the reference
clock before the PLL is considered to be
’Out of Lock’. Hence the acquisition time
is predictable and short and the output
clock CKOUT is always kept within the
500 ppm (2000 ppm) limits ensuring safe
clocking of down stream circuitry.
Lock Detect Circuit
The Lock Detect Circuit continuously
monitors the difference between the ref-
erence clock, which is at 1/16 of the data
rate, and the divided VCO clock. If the
reference clock and the divided VCO fre-
quency differs by more than 500 ppm (or
2000 ppm, selectable), it switches the
PFD into the PLL in order to pull the VCO
back inside the lock-in range. This mode
is called
the acquisition mode.
Once
the VCO is inside the lock-range the
lock-detection circuit switches the Bang-
Bang phase detector into the PLL in or-
der to lock to the data signal. This mode
is called
CDR mode.
The status of the
lock-detection circuit is given by output
pin LOCK. In acquisition mode LOCK is
low.
In acquisition mode
a PFD is used to
ensure predictable lock up conditions for
the GD16504 by locking the VCO to an
external reference clock source. It is only
used during acquisition and pulls the
VCO into the lock range where the Bang-
Bang phase detector is capable of ac-
quiring lock. The PFD is made with digital
set/reset cells giving it a true phase and
frequency characteristic. The reference
clock input, REFCK, to the PFD is at 1/16
of the data rate.
The LOCK Signal
The LOCK output may be used to gener-
ate
Loss of Signal
(LOS). The time for
LOCK to assert is predictable and short,
equal to the time to go into lock, but the
time for LOCK to de-assert must be con-
sidered. When the line is down (i.e. no in-
formation received) the optical receiver
circuit may produce random noise. It is
possible that this random noise will keep
the GD16504 within the 500 ppm
(2000 ppm) range of the line frequency,
hence LOCK will remain asserted for a
non-deterministic time. This may be pre-
vented by injecting a small current at the
loop filter node, which actively pulls the
PLL out of the lock range when the out-
put of the phase detector acts randomly.
The negligible penalty paid is a static
phase error. However, due to the nature
of the phase detector the error will be
Bang-Bang Phase Detector
The Bang-Bang phase detector is used
in
CDR mode
as a true digital type
phase detector, producing a binary out-
put. It samples the incoming data twice
each bit period, once on the transition of
the previous bit period and once in the
middle of the bit period. When a transi-
Data Sheet Rev. 04
GD16504
Page 2
Data Inputs
The input amplifier (pins SIPI / SINI and
SIPO / SINO) is designed as a limiting
amplifier with a sensitivity better than
±20 mV (differential). The inputs may be
either AC or DC coupled. In either case
input termination is made through pins
SIPO / SINO. If the inputs are AC-
coupled the amplifier features an internal
offset cancelling DC feedback path. All
four AC coupling capacitors should be
identical for optimum performance. No-
tice that the offset cancellation will only
work when the input is differential and
AC- coupled as shown in the Figure 3.
SIPI
8k
50R
VTT
SIPO
The GD16504 includes a serial open col-
lector output intended to loop data to
GD16505 as shown in Figure 4 below.
GD16504-68BA
The 68 pin CQFP has a reduced pin
count, this will affect some at the differ-
ential signals that will become single
ended.
The unconnected (inverted) input is bi-
ased to -1.3 V internally on the chip. This
will give the threshold at the single ended
signal.
u
u
+
-
GD16504
SOP
SIP
+
-
GD16505
SON
SIN
Figure 4.
Test Link Connection between
GD16504 and GD16505
Affected signals are:
Inputs: FFIN and REFCK
Output: FP
From LINE
Frame Alignment
The
Frame Detect Alignment
(FDA) cir-
cuit uses the available 48 A1 bytes in the
incoming data stream to align byte wise
and search for valid Frame Sequences
(A1-A1-A2-A2). At the falling edge of the
FFIN signal, the FDA starts looking for
valid A1’s in the incoming data stream,
regardless of byte boundary. To align at
the byte boundary, at least 7 A1’s should
be valid in a row, followed by more than
2 valid A1’s for each erroneous A1.
When the byte alignment is locked, the
FDA asserts FP at the first occurrence of
A1-A1-A2-A2, which must be valid. Note
that the A1 used for byte alignment could
be the same as used for the frame align-
ment, meaning that a sequence of 7 A1’s
followed by 2 A2’s will result in 100%
alignment. When a frame has been found
and the FFIN is not triggered, only frame
sequences (A1-A1-A2-A2) occurring at
the previously aligned byte boundary is
detected. This way the circuit serves two
functions.
When acquiring Frame Alignment, the
assertion of the FFIN / FFINN signal
starts the FDA alignment and when the
first valid sequence is found, the byte
boundary is fixed and the FP / FPN out-
put signal is pulsed. The byte boundary
is held until the next falling edge on FFIN
/ FFINN, and only valid sequences at the
fixed byte boundary will be flagged by the
FP / FPN signal. This allows the user to
control when to align, and to have
flagged all valid sequences once align-
ment is achieved.
Note that all valid sequences (7 A1’s fol-
lowed by 2 A2’s) will be flagged, regard-
less of their mutual distance.
The mean time to align and detect a
frame pulse (BER = 0) is 0.5 x Frame
(62.5
µs),
since the FDA will align and
pulse FP upon reception of the first
Frame Sequence.
+
SINO
50R
-
26dB
8k
VTT
From LINE
SINI
Figure 2.
DC Coupled Input (Ignoring
internal offset compensation)
From LINE
50R
VTT
SIPI
8k
SIPO
+
SINO
50R
-
26dB
8k
VTT
From LINE
SINI
Figure 3.
AC Coupled Input (Using
internal offset compensation)
Following the CDR block the data is 1:16
demultiplexed with frame detect and
alignment, and output together with a
155 MHz clock. The data and clock out-
puts are differential ECL outputs that
should be terminated via 50
Ω
to -2 V.
Data Sheet Rev. 04
GD16504
Page 3
Pin List
Mnemonic:
SIP, SIPO
SIN, SINO
SOP, SON
Pin No.:
144 EA
68 BA
E1, F1
D1, C1
J1, H1
62, 61
63, 64
58, 59
Pin Type:
Anl. IN
Anl. IN
CML OUT
Description:
Loop-through serial positive differential input.
Optimised for max. sensitivity; may be used as ECL input.
Loop-through serial negative differential input.
Optimised for max. sensitivity; may be used as ECL input.
Buffered differential serial data output. High speed Open Col-
lector Drain output to be used in conjunction with GD16505 for
remote/optical loop back. Consult GIGA for information.
Retimed differential data output from DeMUX, bit 15 is the first
received. After frame synchronisation, the data is byte-aligned
with the first A2 byte placed at bit 15 through 8.
When LOCK = “0" or SEL1= ”1" and SEL2 = “0" (LOS),
all outputs will be logic low
DOUT0, DOUN0
DOUT1, DOUN1
DOUT2, DOUN2
DOUT3, DOUN3
DOUT4, DOUN4
DOUT5, DOUN5
DOUT6, DOUN6
DOUT7, DOUN7
DOUT8, DOUN8
DOUT9, DOUN9
DOUT10, DOUN10
DOUT11, DOUN11
DOUT12, DOUN12
DOUT13, DOUN13
DOUT14, DOUN14
DOUT15, DOUN15
REFCK, REFCKN
CKOUT, CKOUN
SEL1, SEL2
A11, A10
B12, A12
D11, C12
D12, E11
F12, F11
G12, G11
H12, H11
J12, J11
L12, K12
M11, M12
M9, M10
L8, L9
M7, M8
M6, L7
M4, M5
L3, M3
A6, A7
A9, B9
A1, E12
12, 11
15, 13
19, 16
22, 20
24, 23
27, 25
29, 28
32, 30
36, 33
39, 37
41, 40
44, 42
46, 45
49, 47
53, 50
56, 54
6, N/A
10, 8
67, 18
ECL OUT
ECL IN
ECL OUT
ECL IN
155 MHz reference clock input. Both biased to -1.3 V in 68BA
version
Regenerated differential output clock, 155 MHz.
Single-ended inputs, PLL set-up of Internal/ External switch
mode and LOCK:
SEL1 SEL2
0
0
Auto lock, 500ppm.
0
1
Global Reset for test purpose only.
1
0
Manual, Phase/ Freq. det, 500 ppm,LOS mode.
1
1
Manual, Phase detector, 2000 ppm.
The LOS mode cause all 16 data outputs, FP and LOCK into
logic low.
FFIN, FFINN
LOCK
B8, A8
B6
7, N/A
5
ECL IN
ECL OUT
Frame FINd signal. A falling edge at this input activates the
frame search. Single ended in 68-pin CQFP.
Single ended CDR Lock alarm output. When low, the divided
VCO freq. deviates more than 500/2000 ppm from REFCK.
When system is unlocked, all 16 data outputs and FP will be
logic low. When SEL1 = "1" and SEL2 = "0" (LOS), the LOCK
will be logic low.
Frame Pulse. One pulse (6.1 ns) indicates that a valid Frame
Sequence has been detected. When LOCK = “0" SEL1 = ”1"
and SEL2 = “0" (LOS), the FP / FPN will be logic low. FP/ FPN
is also low during reset. single ended output in 68-pin CQFP.
Differential in other packages.
VCO control voltage input.
Phase detector or Phase / frequency charge pump output.
DC - functional and parametric test clock input. Bypasses the
VCO when SELTCK is high.
FP, FPN
M1, L1
57, N/A
ECL OUT
VCTL
OUCHP
TCK
A3
A4
A2
2
3
66
Anl. IN
Anl. OUT
ECL IN
Data Sheet Rev. 04
GD16504
Page 4
Mnemonic:
VDD
Pin No.:
144 EA
68 BA
B1, C2, D2, 4, 9, 14, 21,
26, 31, 38,
D4..9, E2,
43, 48, 55,
E4..9, F2,
60, 65
F4..9, G1,
G2, G4..9,
H2, H4..H9,
J2, J4..J9,
K1, K2, M2
C3..5, C10,
D3, D10,
E3, E10,
F3, F10,
G3, G10,
H3, H10,
J3, J10,
K3..5
A5, B5
B3, B4
B2
L2
34, 35, 68
Pin Type:
PWR
Description:
0 V Power for core and ECL I/O.
VEE
PWR
-5 V Power for core and ECL I/O.
VDDA
VEEA
SELTCK
VSOPEN
17
52
1
51
PWR
PWR
PWR
PWR
0 V Power for VCO
-5 V Power for VCO.
Select test clock, for DC test only, connect to VEE.
0 V power for Serial Output (SOP/SON). If output is not used,
VSOPEN may be left open (or connected to VEE), saving
power. Nominal current is 0.5 mA.
Internal reference voltage, leave open
Not used. Reserved for future use.
VCSREF
NC
L6
B7, B10,
B11, C6..9,
C11, K6..9,
K10, K11,
L10, L11,
L4, L5
N/A
N/A
ANALOG
Data Sheet Rev. 04
GD16504
Page 5
嵌入式系统
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