CD54HC107 High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset
| 参数名称 | 属性值 |
| Voltage(Nom)(V) | 3.3,5 |
| F @ nom voltage(Max)(Mhz) | 70 |
| Technology Family | HC |
| Rating | Military |
| IOL(Max)(mA) | -6 |
| IOH(Max)(mA) | 6 |
| VCC(Max)(V) | 6 |
| ICC @ nom voltage(Max)(mA) | 0.04 |
| tpd @ nom Voltage(Max)(ns) | 51 |
| VCC(Min)(V) | 2 |
| Schmitt trigger | No |
| Package Group | CDIP|14 |
| Bits(#) | 2 |
| CD54HC107 | 5962-8515401CA | CD54HC107F3A | CD74HC107 | CD74HCT107 | |
|---|---|---|---|---|---|
| 描述 | CD54HC107 High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset | High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125 | High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset 14-CDIP -55 to 125 | CD74HC107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | CD74HCT107 High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset |
| Voltage(Nom)(V) | 3.3,5 | - | - | 3.3,5 | 5 |
| F @ nom voltage(Max)(Mhz) | 70 | - | - | 70 | 25 |
| Technology Family | HC | - | - | HC | HCT |
| Rating | Military | - | - | Catalog | Catalog |
| IOL(Max)(mA) | -6 | - | - | 6 | 6 |
| IOH(Max)(mA) | 6 | - | - | -6 | -6 |
| VCC(Max)(V) | 6 | - | - | 6 | 5.5 |
| ICC @ nom voltage(Max)(mA) | 0.04 | - | - | 0.04 | 0.04 |
| tpd @ nom Voltage(Max)(ns) | 51 | - | - | 51 | 43 |
| VCC(Min)(V) | 2 | - | - | 2 | 4.5 |
| Schmitt trigger | No | - | - | No | No |
| Package Group | CDIP|14 | - | - | PDIP|14,SOIC|14 | PDIP|14 |
| Bits(#) | 2 | - | - | 2 | 2 |
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