LNK362-364
LinkSwitch-XT
Family
®
Energy Efficient, Low Power
Off-Line Switcher IC
Product Highlights
Optimized for Lowest System Cost
• Proprietary IC trimming and transformer construction
techniques enable
Clampless™
designs with LNK362
for lower system cost, component count and higher
efficiency
• Fully integrated auto-restart for short circuit and
open loop protection
• Self-biased supply – saves transformer auxiliary winding
and associated bias supply components
• Frequency jittering greatly reduces EMI
• Meets HV creepage requirements between DRAIN and
all other pins both on the PCB and at the package
• Lowest component count switcher solution
Features Superior to Linear/RCC
• Accurate hysteretic thermal shutdown protection –
automatic recovery improves
fi
eld reliability
• Universal input range allows worldwide operation
• Simple ON/OFF control, no loop compensation needed
• Eliminates bias winding – simpler, lower cost
transformer
• Very low component count – higher reliability and single
side printed circuit board
• Auto-restart reduces delivered power by 95% during
short circuit and open loop fault conditions
• High bandwidth provides fast turn-on with no overshoot
and excellent transient load response
EcoSmart
– Extremely Energy-Efficient
• Easily meets all global energy efficiency regulations with
no added components
• No-load consumption
<300
mW without bias winding at
265 VAC input (<50 mW with bias winding)
• ON/OFF control provides constant efficiency to very
light loads – ideal for mandatory CEC regulations
®
+
DC
Output
+
Wide Range
HV DC Input
LinkSwitch-XT
LNK362
D
FB
BP
S
a) Clampless
fl
yback converter with LNK362
PI-4086-081005
+
DC
Output
+
Wide Range
HV DC Input
LinkSwitch-XT
LNK363-364
D
FB
BP
S
b) Flyback converter with LNK363/4
PI-4061-081005
Figure 1. Typical Application with LinkSwitch-XT.
OUTPUT POWER TABLE
(4)
230 VAC ±15%
85-265 VAC
PRODUCT
(3)
LNK362P/G/D
LNK363P/G/D
LNK364P/G/D
Adapter
(1)
2.8 W
5W
5.5 W
Open
Open
Adapter
(1)
Frame
(2)
Frame
(2)
2.8 W
7.5 W
9W
2.6 W
3.7 W
4W
2.6 W
4.7 W
6W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed
adapter measured at 50 °C ambient.
2. Minimum practical continuous power in an open frame design
with adequate heat sinking, measured at 50 °C ambient.
3. Packages: P: DIP-8B, G: SMD-8B, D: SO-8C. Please see Part
Ordering Information.
4. See Key Application Considerations section for complete description
of assumptions.
Applications
• Chargers/adapters for cell/cordless phones, PDAs, digital
cameras, MP3/portable audio players, and shavers
• Supplies for appliances, industrial systems, and metering
Description
LinkSwitch-XT
incorporates a 700 V power MOSFET, oscillator,
simple ON/OFF control scheme, a high-voltage switched current
source, frequency jittering, cycle-by-cycle current limit and
thermal shutdown circuitry onto a monolithic IC. The startup
and operating power are derived directly from the DRAIN
pin, eliminating the need for a bias winding and associated
circuitry.
November 2008
LNK362-364
BYPASS
(BP)
DRAIN
(D)
REGULATOR
5.8 V
FAULT
PRESENT
AUTO-
RESTART
COUNTER
CLOCK
RESET
6.3 V
5.8 V
4.8 V
BYPASS PIN
UNDER-VOLTAGE
+
-
CURRENT LIMIT
COMPARATOR
+
-
VI
LIMIT
JITTER
CLOCK
DC
MAX
OSCILLATOR
FEEDBACK
(FB)
V
FB
-V
TH
S
R
Q
Q
LEADING
EDGE
BLANKING
THERMAL
SHUTDOWN
SOURCE
(S)
PI-4232-110205
Figure 2. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
Power MOSFET drain connection. Provides internal operating
current for both startup and steady-state operation.
BYPASS (BP) Pin:
Connection point for a 0.1
μF
external bypass capacitor for the
internally generated 5.8 V supply. If an external bias winding is
used, the current into the BP pin must not exceed 1 mA.
FEEDBACK (FB) Pin:
During normal operation, switching of the power MOSFET is
controlled by this pin. MOSFET switching is disabled when a
current greater than 49
μA
is delivered into this pin.
SOURCE (S) Pin:
This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.
P Package (DIP-8B)
G Package (SMD-8B)
S
S
BP
FB
D Package (SO-8C)
1
2
3
4
3a
8
7
S
S
BP
FB
D
1
2
8
7
6
S
S
S
S
4
5
5
D
3b
PI-3491-120706
Figure 3. Pin Configuration.
2-2
2
2
Rev. E 11/08
LNK362-364
LinkSwitch-XT
Functional Description
LinkSwitch-XT
combines a high-voltage power MOSFET
switch with a power supply controller in one device. Unlike
conventional PWM (pulse width modulator) controllers, a
simple ON/OFF control regulates the output voltage. The
controller consists of an oscillator, feedback (sense and logic)
circuit, 5.8 V regulator, BYPASS pin undervoltage circuit,
over-temperature protection, frequency jittering, current limit
circuit, and leading edge blanking integrated with a 700 V
power MOSFET. The
LinkSwitch-XT
incorporates additional
circuitry for auto-restart.
Oscillator
The typical oscillator frequency is internally set to an average
of 132 kHz. Two signals are generated from the oscillator: the
maximum duty cycle signal (DC
MAX
) and the clock signal that
indicates the beginning of each cycle.
The oscillator incorporates circuitry that introduces a small
amount of frequency jitter, typically 9 kHz peak-to-peak,
to minimize EMI emission. The modulation rate of the
frequency jitter is set to 1.5 kHz to optimize EMI reduction
for both average and quasi-peak emissions. The frequency
jitter should be measured with the oscilloscope triggered at
the falling edge of the DRAIN waveform. The waveform in
Figure 4 illustrates the frequency jitter.
Feedback Input Circuit
The feedback input circuit at the FB pin consists of a low
impedance source follower output set at 1.65 V for LNK362
and 1.63 V for LNK363/364. When the current delivered into
this pin exceeds 49
μA,
a low logic level (disable) is generated
at the output of the feedback circuit. This output is sampled
at the beginning of each cycle on the rising edge of the clock
signal. If high, the power MOSFET is turned on for that cycle
(enabled), otherwise the power MOSFET remains off (disabled).
Since the sampling is done only at the beginning of each cycle,
subsequent changes in the FB pin voltage or current during the
remainder of the cycle are ignored.
5.8 V Regulator and 6.3 V Shunt Voltage Clamp
The 5.8 V regulator charges the bypass capacitor connected to the
BYPASS pin to 5.8 V by drawing a current from the voltage on
the DRAIN, whenever the MOSFET is off. The BYPASS pin is
the internal supply voltage node. When the MOSFET is on, the
LinkSwitch-XT
runs off of the energy stored in the bypass capacitor.
Extremely low power consumption of the internal circuitry allows
the device to operate continuously from the current drawn from
the DRAIN pin. A bypass capacitor value of 0.1
μF
is sufficient
for both high frequency decoupling and energy storage.
In addition, there is a 6.3 V shunt regulator clamping the
BYPASS pin at 6.3 V when current is provided to the BYPASS
pin through an external resistor. This facilitates powering of
the device externally through a bias winding to decrease the
no-load consumption to less than 50 mW.
BYPASS Pin Undervoltage
The BYPASS pin undervoltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.8 V.
Once the BYPASS pin voltage drops below 4.8 V, it must rise
back to 5.8 V to enable (turn-on) the power MOSFET.
Over-Temperature Protection
The thermal shutdown circuitry senses the die temperature.
The threshold is set at 142
°C
typical with a 75
°C
hysteresis.
When the die temperature rises above this threshold (142
°C)
the
power MOSFET is disabled and remains disabled until the die
temperature falls by 75
°C,
at which point it is re-enabled.
Current Limit
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (I
LIMIT
), the
power MOSFET is turned off for the remainder of that cycle.
The leading edge blanking circuit inhibits the current limit
comparator for a short time (t
LEB
) after the power MOSFET
is turned on. This leading edge blanking time has been set so
that current spikes caused by capacitance and rectifier reverse
recovery time will not cause premature termination of the
switching pulse.
Auto-Restart
In the event of a fault condition such as output overload, output
short circuit, or an open loop condition,
LinkSwitch-XT
enters
into auto-restart operation. An internal counter clocked by the
oscillator gets reset every time the FB pin is pulled high. If the
FB pin is not pulled high for approximately 40 ms, the power
MOSFET switching is disabled for 800 ms. The auto-restart
alternately enables and disables the switching of the power
MOSFET until the fault condition is removed.
PI-4047-110205
600
500
400
300
200
100
0
136.5 kHz
127.5 kHz
V
DRAIN
0
5
10
Time (μs)
Figure 4. Frequency Jitter.
2-3
3
Rev. E 11/08
LNK362-364
CY1
100 pF
250 VAC
L1
1 mH
T1
EE16 9
C4
330
μF
16 V
D5
1N4934
8
NC NC
D1
1N4005
D2
1N4005
R1
3.9 k
1/8 W
VR1
BZX79-
B5V1
5.1 V, 2%
R2
390
Ω
1/8 W
J4
6.2 V,
322 mA
J3
4
5
3
J1
RF1
8.2
Ω
2.5 W
85-265
VRMS
C1
3.3
μF
400 V
C2
3.3
μF
400 V
J2
LinkSwitch-XT
U1
LNK362P
D3
1N4005
D4
1N4005
D
FB
BP
U2
PC817A
R3
1k
1/8 W
S
L2
1 mH
C3
100 nF
50 V
PI-4162-110205
Figure 5. 2 W Universal Input CV Adapter Using LNK362.
Applications Example
A 2 W CV Adapter
The schematic shown in Figure 5 is a typical implementation of
a universal input, 6.2 V
±7%,
322 mA adapter using LNK362.
This circuit makes use of the
Clampless
technique to eliminate the
primary clamp components and reduce the cost and complexity
of the circuit.
The
EcoSmart
features built into the
LinkSwitch-XT
family
allow this design to easily meet all current and proposed
energy efficiency standards, including the mandatory California
Energy Commission (CEC) requirement for average operating
efficiency.
The AC input is rectified by D1 to D4 and
fi
ltered by the bulk
storage capacitors C1 and C2. Resistor RF1 is a
fl
ameproof,
fusible, wire wound type and functions as a fuse, inrush current
limiter and, together with the
π
fi
lter formed by C1, C2, L1
and L2, differential mode noise attenuator. Resistor R1 damps
ringing caused by L1 and L2.
This simple input stage, together with the frequency jittering of
LinkSwitch-XT,
a low value Y1 capacitor and PI’s
E-Shield™
windings within T1, allow the design to meet both conducted
and radiated EMI limits with
>10
dBμV margin. The low value
of CY1 is important to meet the requirement for a very low
touch current (the line frequency current that
fl
ows through
CY1) often specified for adapters, in this case
<10 μA.
2-4
4
4
Rev. E 11/08
The rectified and
fi
ltered input voltage is applied to the primary
winding of T1. The other side of the primary is driven by the
integrated MOSFET in U1. No primary clamp is required as the
low value and tight tolerance of the LNK362 internal current
limit allows the transformer primary winding capacitance to
provide adequate clamping of the leakage inductance drain
voltage spike.
The secondary of the
fl
yback transformer T1 is rectified by D5,
a low cost, fast recovery diode, and
fi
ltered by C4, a low ESR
capacitor. The combined voltage drop across VR1, R2 and the
LED of U2 determines the output voltage. When the output
voltage exceeds this level, current will
fl
ow through the LED
of U2. As the LED current increases, the current fed into the
FEEDBACK pin of U1 increases until the turnoff threshold
current (~49
μA)
is reached, disabling further switching cycles
of U1. At full load, almost all switching cycles will be enabled,
and at very light loads, almost all the switching cycles will be
disabled, giving a low effective frequency and providing high
light load efficiency and low no-load consumption.
Resistor R3 provides 1 mA through VR1 to bias the Zener
closer to its test current. Resistor R2 allows the output voltage
to be adjusted to compensate for designs where the value of the
Zener may not be ideal, as they are only available in discrete
voltage ratings. For higher output accuracy, the Zener may be
replaced with a reference IC such as the TL431.
LNK362-364
The
LinkSwitch-XT
is completely self-powered from the DRAIN
pin, requiring only a small ceramic capacitor C3 connected to
the BYPASS pin. No auxiliary winding on the transformer is
required.
2. For designs where P
O
≤
2 W, a two-layer primary should be
used to ensure adequate primary intra-winding capacitance
in the range of 25 pF to 50 pF.
3. For designs where 2
<
P
O
≤
2.5 W, a bias winding should be
added to the transformer using a standard recovery rectifier
diode to act as a clamp. This bias winding may also be used
to externally power the device by connecting a resistor from
the bias-winding capacitor to the BYPASS pin. This inhibits
the internal high-voltage current source, reducing device
dissipation and no-load consumption.
4. For designs where P
O
>
2.5 W
Clampless
designs are not
practical and an external RCD or Zener clamp should be
used.
5. Ensure that worst-case high line, peak drain voltage is below
the BV
DSS
specification of the internal MOSFET and ideally
≤
650 V to allow margin for design variation.
†For 110 VAC only input designs it may be possible to extend
the power range of
Clampless
designs to include the LNK363.
However, the increased leakage ringing may degrade EMI
performance.
**V
OR
is the secondary output plus output diode forward voltage
drop that is reflected to the primary via the turns ratio of the
transformer during the diode conduction time. The V
OR
adds
to the DC bus voltage and the leakage spike to determine the
peak drain voltage.
Audible Noise
The cycle skipping mode of operation used in
LinkSwitch-XT
can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
be designed such that the peak core
fl
ux density is below
1500 Gauss (150 mT). Following this guideline and using the
standard transformer production technique of dip varnishing
practically eliminates audible noise. Vacuum impregnation
of the transformer should not be used due to the high primary
capacitance and increased losses that result. Higher
fl
ux densities
are possible, however careful evaluation of the audible noise
performance should be made using production transformer
samples before approving the design.
Ceramic capacitors that use dielectrics, such as Z5U, when
used in clamp circuits may also generate audio noise. If this is
the case, try replacing them with a capacitor having a different
dielectric or construction, for example a
fi
lm type.
LinkSwitch-XT
Layout Considerations
See Figure 6 for a recommended circuit board layout for
LinkSwitch-XT
(P & G package).
Single Point Grounding
Use a single point ground connection from the input
fi
lter capacitor
to the area of copper connected to the SOURCE pins.
2-5
5
Rev. E 11/08
Key Application Considerations
LinkSwitch-XT
Design Considerations
Output Power Table
The data sheet maximum output power table (Table 1) represents
the maximum practical continuous output power level that can
be obtained under the following assumed conditions:
1. The minimum DC input voltage is 90 V or higher for 85 VAC
input, or 240 V or higher for 230 VAC input or 115 VAC
with a voltage doubler. The value of the input capacitance
should be large enough to meet these criteria for AC input
designs.
2. Secondary output of 6 V with a fast PN rectifier diode.
3. Assumed efficiency of 70%.
4. Voltage only output (no secondary-side constant current
circuit).
5. Discontinuous mode operation (K
P
>1).
6. A primary clamp (RCD or Zener) is used.
7. The part is board mounted with SOURCE pins soldered
to a sufficient area of copper to keep the SOURCE pin
temperature at or below 100 °C.
8. Ambient temperature of 50 °C for open frame designs
and an internal enclosure temperature of 60 °C for adapter
designs.
Below a value of 1, K
P
is the ratio of ripple to peak primary
current. Above a value of 1, K
P
is the ratio of primary MOSFET
OFF time to the secondary diode conduction time. Due to
the
fl
ux density requirements described below, typically a
LinkSwitch-XT
design will be discontinuous, which also has
the benefits of allowing lower cost fast (instead of ultra-fast)
output diodes and reducing EMI.
Clampless
Designs
Clampless
designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source
voltage. Therefore, the maximum AC input line voltage, the
value of V
OR
, the leakage inductance energy, a function of
leakage inductance and peak primary current, and the primary
winding capacitance determine the peak drain voltage. With no
significant dissipative element present, as is the case with an
external clamp, the longer duration of the leakage inductance
ringing can increase EMI.
The following requirements are recommended for a universal
input or 230 VAC only
Clampless
design:
1. A
Clampless
design should only be used for P
O
≤
2.5 W,
using the LNK362
†
and a V
OR
**
≤
90 V.
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