32K x 8
Radiation Hardened Programmable
Read Only Memory (PROM) – 5 V
Features
197A807
Product Description
Other
• Read/Write Cycle Times
≤45
ns (-55 °C to 125°C)
• SMD Number 5962R96891
• Asynchronous Operation
• CMOS or TTL Compatible I/O
• Single 5 V ±10% Power Supply
• Low Operating Power
• Packaging Options
• 28-Lead Flat Pack (0.500” x 0.720”)
Radiation
• Fabricated with Bulk CMOS 0.8 µm Process
• Total Dose Hardness through 2x10
5
rad(Si)
• Neutron Hardness through 1x10
12
N/cm
2
• SEU Immune (No Latches)
• Latchup Free
General Description
The 32K x 8 radiation hardened PROM is
pinout, function and package compatible with
commercial 28C256 series 32K x EEPROMs,
such as SEEQ 28C256 and Atmel AT28C256.
The PROM is fabricated with BAE SYSTEMS’
QML-qualified radiation hardened technology,
and is designed for use in systems operating in
radiation environments.
The radiation hardened
Oxide-Nitride-Oxide (ONO) anti-fuse technology
features 0.8 micron, 5 V transistors in the data
path, and 1.0 micron, high voltage N and PFETs
in the programming path circuitry. The PROM
operates over the full military temperature
range, requires a single 5 V ±10% power
supply, and is available with either TTL or
CMOS compatible I/O. Power consumption is
typically 15 mW/MHz in operation and is less
than 10 mW/MHz in the low power disabled
mode. The PROM operation is fully
asynchronous, with an associated typical
access time of 27 nanoseconds. Synchronous
operation is also possible using CE as a clock.
BAE SYSTEMS’ enhanced bulk CMOS
technology is radiation hardened through the
use of advanced and proprietary design, layout,
and process hardening techniques.
BAE SYSTEMS • 9300 Wellington Road • Manassas, Virginia 20110-4122
Functional Diagram
A5 - A11
Row Decoders
Memory Array
A0 - A4
A12 - A14
CE
OE
VPP*
Column Decoders
Section Select
Column Muxing
and
Sense Amps
Control Logic
I/O Buffers
DQ0 - 7
*PROM Programming Voltage
Signal Definitions
A: 0-14
– Address input pins that select a particular
eight-bit word within the memory array.
– Bi-directional data pins that serve as data
outputs during a read operation and as data
inputs during a write operation.
– Negative output enable, when at a high level,
holds the data output drivers in a high
impedance state. In programming mode, with
OE high and CE low, data driver state is in
“Data-In” to enable programming.
CE
DQ: 0-7
– Chip enable, when at a low level with OE at low
level, allows normal operation. When at a high
level, CE forces the data output drivers in a high
impedance state.
OE
Truth Table
Mode
Read
Tristate
Standby
Standby
Program
Inputs
(1),(2)
CE
Low
Low
V
DD
High
Low
OE
Low
High
X
X
High
VPP
V
DD
V
DD
V
DD
V
DD
17V ± 0.5V
I/O
Data-Out
High-Z
High-Z
High-Z
Data-In
Power
(3)
Active
Active
Standby1
Standby2
Programming
Notes:
1) V
IN
for don’t care (X) inputs = V
IL
or V
IH
.
2) High: V
IN
≥
2.2 V for TTL inputs. V
IN
≥
3.5 V for CMOS inputs.
Low: V
IN
≤
0.8 V for TTL inputs. V
IN
≤
1.5 V for CMOS inputs.
3) Minimum I
DD
is drawn when standby mode is implemented with
CE = V
DD
(standby1 power).
2
Absolute Maximum Ratings
Applied Conditions
(1)
Storage Temperature Range (Ambient)
Operating Temperature Range (T
CASE
)
Positive Supply Voltage
Input Voltage
(2)
Output Voltage
(2)
Power Dissipation
(3)
Lead Temperature (Soldering 5 sec)
Electrostatic Discharge Sensitivity
(4)
Notes:
Minimum
-65°C
-55°C
-0.5 V
-0.5 V
-0.5 V
Maximum
+150°C
+125°C
+7.0 V
V
DD
+ 0.5 V
V
DD
+ 0.5 V
1.5 W
+250°C
(Class I)
1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.
2) Maximum applied voltage shall not exceed +7.0 V.
3) Guaranteed by design; not tested.
4) Class as defined in MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol
V
DD
V
PP
GND
T
C
V
IL
V
IH
Parameters
(1)
Supply Voltage
Programming Voltage
Supply Voltage Reference
Case Temperature
Input Logic “Low” - CMOS
Input Logic “Low” - TTL
Input Logic “High” - CMOS
Input Logic “High” - TTL
Notes:
Minimum
+4.5
V
DD
(2)
0.0
-55
0.0
0.0
+3.5
+2.2
Maximum
+5.5
V
DD
(2)
0.0
+125
+1.5
+0.8
V
DD
V
DD
Units
Volt
Volt
Volt
Celsius
Volt
Volt
1) All voltages referenced to GND.
2) V
PP
= V
DD
during non-programming mode.
Power Sequencing
Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:
• Power-Up Sequence: GND, V
DD
, Inputs
• Power-Down Sequence: Inputs, V
DD
, GND
3
DC Electrical Characteristics
Group A
Subgroups
1, 2, 3
Device
Type
(2)
All
Limits
Minimum Maximum
150
Test
Supply Current
(Cycling Selected)
Supply Current
(Standby)
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
TTL Inputs
Low Level Input Voltage
TTL Inputs
High Level Input Voltage
CMOS Inputs
Low Level Input Voltage
CMOS Inputs
Input Leakage
Output Leakage
C
in
C
out
Symbol
Test Conditions
(1)
F = F
MAX
= 1/t
AVAV(min)
CMOS Input
No Output Load
F = F
MAX
= 1/t
AVAV(min)
CE = V
PP
= V
IH
= V
DD
I
OH
= -2 mA
I
OH
= -200 µA
I
OL
= 4 mA
I
OL
= 200 µA
Units
I
DD1
mA
I
DD2
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
I
ILK
I
OLK
1, 2, 3
All
4.2
V
DD
- 0.1 V
2.0
mA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
All
All
xxxT
xxxT
xxxC
xxxC
All
All
All
All
V
0.4
0.1
V
V
0.8
V
V
1.5
V
µA
µA
pF
pF
2.2
3.5
0 V
≤
V
IN
≤
5.5 V
0 V
≤
V
OUT
≤
5.5 V
(3)
1, 2, 3
1, 2, 3
4
4
-5
-10
5
10
7
10
(3)
Note:
1) -55 °C
≤
T
case
≤
+125°C; 4.5 V
≤
V
DD
≤
5.5 V; unless otherwise
specified.
Test conditions for AC measurements:
2) The delineation in this table is by input device type (TTL or
CMOS). xxxT represents a device with TTL inputs; xxxC
represents a device with CMOS inputs.
3) Measured during initial device characterization.
•
Input Levels
•
Input Rise and Fall Time
•
Input and Output Timing
Reference Levels (Except
for Tristate Parameters)
•
Input and Output Timing
Reference Levels or
Tristate Parameters
•
Programmed Array Mix of
‘1’s and ‘0’s
•
Output Load
•
Read Cycle
–
0 V to V
DD
–
≤
2.0 ns/Volt
–
2.5 V
–
V
OL
= 0.5 V;
V
OH
= V
DD
- 0.5 V
–
50%
Output Load Circuit
300
Ω
± 10%
2.8V
–
See Output Load Circuit
Diagram
–
See Read Cycle Timing
50 pF ± 10%
4
Read Cycle AC Timing Characteristics
(1)
Limits
Minimum
Maximum
45
60
45
60
45
60
45
60
0
0
0
15
15
Test
Read Cycle Time
Address Access Time
Symbol
t
AVAV
t
AVQV
t
ELQV
Device Type
X4XX
X6XX
X4XX
X6XX
X4XX
X6XX
X4XX
X6XX
Units
ns
ns
Chip Enable Access Time
ns
Output Enable Access Time
Chip Enable to Output Active
Output Enable to Output Active
Output Hold After Address Change
Chip Enable to Output Disable
Output Enable to Output Disable
Note:
t
GLQV
t
ELQX
t
GLQX
t
AXQX
t
EHQZ
t
GHQZ
ns
ns
ns
ns
ns
ns
1) Test Conditions: -55°C
≤
T
case
≤
+125°C; 4.5 V
≤
V
DD
≤
5.5 V; unless otherwise specified.
Read Cycle Timing Diagram
t
AVAV
Address
Valid Address
t
AVQV
t
ELQV
t
AXQX
CE
t
ELQX
t
GLQV
OE
t
EHQZ
t
GLQX
Data
Out
t
GHQZ
Valid Data
High Impedance
5
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