The CAT5409 serial clock input pin is used to clock
all data transfers into or out of the device.
SDA:
Serial Data
The CAT5409 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-
Ored with the other open drain or open collector
outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when ad-
dressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with the
address input in order to initiate communication
with the CAT5409.
R
H
, R
L
: Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to
the terminal connections on a mechanical potenti-
ometer.
R
W
:
Wiper
The four R
W
pins are equivalent to the wiper
terminal of a mechanical potentiometer.
WP:
Write Protect Input
The
WP
pin when tied low prevents non-volatile
writes to the data registers (change of wiper control
register is allowed) and when tied high or left
floating normal read/write operations are allowed.
See
Write Protection
on page 7 for more details.
DEVICE OPERATION
The CAT5409 is four resistor arrays integrated with 2-
wire serial interface logic, four 6-bit wiper control
registers and sixteen 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed terminals
of a mechanical potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and may be interchanged. The tap
positions between and at the ends of the series resistors
are connected to the output wiper terminals (R
W
) by a
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the 2-wire bus. Additional instructions allows data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
Document No. 2010, Rev. I
2
CAT5409
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)(2)
................ -2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current .................................................. +12mA
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Recommended Operating Conditions:
V
CC
= +2.5V to +6.0V
Temperature
Industrial
Min
-40°C
Max
85°C
Notes:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(2)
Relative Linearity
(3)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
w(n)(actual)
-R
(n)(expected)(5)
R
w(n+1)
-[R
w(n)+LSB
]
(5)
(1)
(1)
(1)
R
POT
= 50kΩ
(1)
10/10/25
0.4
+300
20
I
W
= +3mA @ V
CC
=3V
I
W
= +3mA @ V
CC
= 5V
V
SS
= 0V
(1)
GND
TBD
1.6
+1
+0.2
80
25°C, each pot
Test Conditions
Min
Typ
100
50
10
2.5
+20
1
50
+6
300
150
V
CC
Max
Units
kΩ
kΩ
kΩ
kΩ
%
%
mW
mA
Ω
Ω
V
nV/ Hz
%
LSB
(4)
LSB
(4)
ppm/°C
ppm/°C
pF
MHz
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = R
TOT
/ 63 or (R
H
- R
L
) / 63, single pot
(5) n = 0, 1, 2, ..., 63
3
Document No. 2010, Rev. I
CAT5409
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Test Conditions
f
SCL
= 400kHz
V
IN
= GND or V
CC;
SDA Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Typ
Max
1
1
10
10
Units
mA
µA
µA
µA
V
V
V
-1
V
CC
x 0.7
I
OL
= 3 mA
V
CC
x 0.3
V
CC
+ 1.0
0.4
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL,
WP)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
f
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Min
Typ
Max
400
50
0.9
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
1.2
0.6
1.2
0.6
0.6
0
100
0.3
300
0.6
50
POWER UP TIMING
(1)
Over recommended operating conditions unless otherwise stated.
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 2010, Rev. I
4
CAT5409
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,
the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)(2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
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