OMC942723072
Hitachi Single-Chip Microcomputer
H8/538,
H8/539
Hardware Manual
2nd Edition
Preface
The H8/538 and H8/539 are original Hitachi high-performance single-chip microcontrollers with a
high-speed 16-bit H8/500 CPU core and extensive on-chip peripheral functions. They are suitable
for controlling a wide range of medium-scale office and industrial equipment and consumer
products.
The general-register architecture and highly orthogonal, optimized instruction set of the H8/500
CPU enable even programs coded in the high-level C language to be compiled into efficient object
code.
Many of the peripheral functions needed in microcontroller application systems are provided on-
chip, including large RAM and ROM, a powerful set of timers, a serial interface, a high-precision
A/D converter, and I/O ports. Compact, high-performance systems can be implemented easily.
The H8/538 and H8/539 are available with mask-programmable ROM for full-scale volume
production, and in ZTAT™ (zero turn-around time) versions with on-chip PROM for products
with frequent design changes, or for the early stages of volume production.
This document describes the H8/538 and H8/539 hardware. For further details about the H8/500
CPU instruction set, refer to the
H8/500 Series Programming Manual.
Note: ZTAT™ is a registered trademark of Hitachi, Ltd.
Contents
Section 1
1.1
1.2
1.3
Overview
.......................................................................................................
Features ..........................................................................................................................
Block Diagram ...............................................................................................................
Pin Descriptions .............................................................................................................
1.3.1 Pin Arrangement ..............................................................................................
1.3.2 Pin Functions ....................................................................................................
1
1
5
7
7
9
Section 2
2.1
Operating Modes
........................................................................................ 21
21
21
22
23
24
24
24
24
24
24
24
25
26
26
28
2.2
2.3
2.4
2.5
Overview ........................................................................................................................
2.1.1 Selection of Operating Mode ...........................................................................
2.1.2 Register Configuration .....................................................................................
Mode Control Register ..................................................................................................
Operating Mode Descriptions ........................................................................................
2.3.1 Mode 1 (Expanded Minimum Mode) ..............................................................
2.3.2 Mode 2 (Expanded Minimum Mode) ..............................................................
2.3.3 Mode 3 (Expanded Maximum Mode) ..............................................................
2.3.4 Mode 4 (Expanded Maximum Mode) ..............................................................
2.3.5 Modes 5 and 6 ..................................................................................................
2.3.6 Mode 7 (Single-Chip Mode) ............................................................................
Pin Functions in Each Operating Mode .........................................................................
Memory Map in Each Mode ..........................................................................................
2.5.1 H8/538 Memory Maps ......................................................................................
2.5.2 H8/539 Memory Maps ......................................................................................
Section 3
3.1
CPU
................................................................................................................ 31
31
31
32
34
35
35
35
35
35
36
36
36
36
37
3.2
3.3
Overview ........................................................................................................................
3.1.1 Features ............................................................................................................
3.1.2 Address Space ..................................................................................................
3.1.3 Programming Model ........................................................................................
General Registers ...........................................................................................................
3.2.1 Overview ..........................................................................................................
3.2.2 Register Configuration .....................................................................................
3.2.3 Stack Pointer ....................................................................................................
3.2.4 Frame Pointer ...................................................................................................
Control Registers ...........................................................................................................
3.3.1 Overview ..........................................................................................................
3.3.2 Register Configuration .....................................................................................
3.3.3 Program Counter ..............................................................................................
3.3.4 Status Register ..................................................................................................
3.4
3.5
3.6
3.7
3.8
3.9
3.10
Page Registers ................................................................................................................
3.4.1 Overview ..........................................................................................................
3.4.2 Register Configuration .....................................................................................
3.4.3 Code Page Register ..........................................................................................
3.4.4 Data Page Register ...........................................................................................
3.4.5 Extended Page Register ....................................................................................
3.4.6 Stack Page Register ..........................................................................................
Base Register .................................................................................................................
3.5.1 Overview ..........................................................................................................
3.5.2 Register Configuration .....................................................................................
Data Formats ..................................................................................................................
3.6.1 Data Formats in General Registers ..................................................................
3.6.2 Data Formats in Memory .................................................................................
3.6.3 Stack Data Formats ..........................................................................................
Addressing Modes and Effective Address Calculation .................................................
3.7.1 Addressing Modes ............................................................................................
3.7.2 Effective Address Calculation ..........................................................................
Operating Modes ...........................................................................................................
3.8.1 Minimum Mode ...............................................................................................
3.8.2 Maximum Mode ...............................................................................................
Basic Operational Timing ..............................................................................................
3.9.1 Overview ..........................................................................................................
3.9.2 Access to On-Chip Memory .............................................................................
3.9.3 Access to Two-State-Access Address Space ....................................................
3.9.4 Access to On-Chip Supporting Modules .........................................................
3.9.5 Access to Three-State-Access Address Space .................................................
CPU States .....................................................................................................................
3.10.1 Overview ..........................................................................................................
3.10.2 Program Execution State ..................................................................................
3.10.3 Exception-Handling State ................................................................................
3.10.4 Bus-Released State ...........................................................................................
3.10.5 Reset State ........................................................................................................
3.10.6 Power-Down State ...........................................................................................
40
40
41
41
42
42
42
43
43
43
44
44
45
45
46
46
50
52
52
52
52
53
53
54
55
56
58
58
59
59
60
68
68
Section 4
4.1
Exception Handling
................................................................................... 69
69
69
70
71
73
73
4.2
Overview ........................................................................................................................
4.1.1 Exception Handling Types and Priority ...........................................................
4.1.2 Exception Handling Operation .........................................................................
4.1.3 Exception Sources and Vector Table ................................................................
Reset ...........................................................................................................................
4.2.1 Overview ..........................................................................................................
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.2.2 Reset Sequence ................................................................................................
4.2.3 Interrupts after Reset ........................................................................................
Address Error .................................................................................................................
4.3.1 Address Error in Instruction Prefetch ..............................................................
4.3.2 Address Error in Word Data Access ................................................................
4.3.3 Address Error in Single-Chip Mode ................................................................
Trace ...........................................................................................................................
Interrupts ........................................................................................................................
Invalid Instructions ........................................................................................................
Trap Instructions and Zero Divide .................................................................................
Cases in which Exception Handling is Deferred ...........................................................
4.8.1 Instructions that Disable Exception Handling .................................................
4.8.2 Disabling of Exceptions Immediately after a Reset .........................................
4.8.3 Disabling of Interrupts after a Data Transfer Cycle .........................................
Stack Status after Completion of Exception Handling ..................................................
4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions,
and Zero Divide Exceptions .............................................................................
4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction .............
Notes on Use of the Stack ..............................................................................................
73
76
76
77
77
78
81
81
82
83
84
84
85
85
86
87
87
87
Section 5
5.1
H8 Multiplier (H8/539 Only)
................................................................... 89
89
89
90
91
92
92
94
94
94
95
95
95
96
96
97
97
97
98
98
99
5.2
5.3
Overview.........................................................................................................................
5.1.1 Features .............................................................................................................
5.1.2 Block Diagram ..................................................................................................
5.1.3 Register Configuration ......................................................................................
Register Descriptions......................................................................................................
5.2.1 MULT Control Register ....................................................................................
5.2.2 MULT Base Address Register...........................................................................
5.2.3 MULT Multiplier Address Register ..................................................................
5.2.4 MULT Multiplicand Address Register..............................................................
5.2.5 MULT Multiplier Register A ............................................................................
5.2.6 MULT Multiplier Register B.............................................................................
5.2.7 MULT Multiplier Register C.............................................................................
5.2.8 MULT Immediate Multiplier Register ..............................................................
5.2.9 MULT Immediate Multiplicand Register..........................................................
5.2.10 MULT Result Register, Extended High Word ..................................................
5.2.11 MULT Result Register, High Word...................................................................
5.2.12 MULT Result Register, Low Word ...................................................................
Operation ........................................................................................................................
5.3.1 Initialization of MULT Result Registers...........................................................
5.3.2 Writing to MULT Multiplier Registers .............................................................
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