DAC5670-SP
www.ti.com...............................................................................................................................................................................................
SGLS386 – JANUARY 2009
14-BIT 2.4-GSPS DIGITAL-TO-ANALOG CONVERTER
1
FEATURES
•
•
•
•
•
•
•
•
14-Bit Resolution
•
2.4-GSPS Maximum Update Rate Digital to
Analog Converter
•
Dual Differential Input Ports
– Even/Odd Demultiplexed Data
– Maximum 1.2 GSPS Each Port, 2.4 GSPS
Total
– Dual 14-Bit Inputs + 1 Reference Bit
– DDR Output Clock
– DLL Optimized Clock Timing Synchronized
to Reference Bit
– LVDS and HyperTransport™ Voltage Level
Compatible
– Internal 100-Ω Terminations for Data and
Reference Bit Inputs
•
Selectable 2 Times Interpolation With Fs/2
Mixing
2
Differential Scalable Current Outputs:
5 mA to 30 mA
On-Chip 1.2-V Reference
3.3-V Analog Supply Operation
Power Dissipation: 2 W
192-Ball CBGA (GEM) Package
QML-V Qualified, SMD 5962-07247
Military Temperature Range
(-55°C to 125°C T
case
)
APPLICATIONS
•
•
Cable Modem Termination System Direct
Synthesis
Cellular Base Transceiver Station Transmit
Channels
– CDMA: W-CDMA, CDMA2000, TD-SCDMA
– 800 to 900-MHz Direct Synthesis
Point-to-Point Microwave
Radar
Satellite Communications
•
•
•
DESCRIPTION
The DAC5670 is a 14-bit 2.4-GSPS digital-to-analog converter (DAC) with dual demultiplexed differential input
ports. The DAC5670 is clocked at the DAC sample rate and the two input ports run at a maximum of 1.2 GSPS.
An additional reference bit input sequence is used to adjust the output clock delay to the data source, optimizing
the internal data latching clock relative to this reference bit with a delay lock loop (DLL).
The DAC5670 also can accept data up to 1.2 GSPS on one input port the same clock configuration. In the single
port mode, repeating the input sample (A_ONLY mode), 2 times interpolation by zero stuff (A_ONLY_ZS mode),
or 2 times interpolation by repeating and inverting the input sample (A_ONLY_INV) are used to double the input
sample rate up to 2.4 GSPS.
The DAC5670 operates with a single 3-V to 3.6-V supply voltage. Power dissipation is 2 W at maximum
operating conditions. The DAC5670 provides a nominal full-scale differential current-output of 20 mA, supporting
both single-ended and differential applications. An on-chip 1.2-V temperature-compensated bandgap reference
and control amplifier allows the user to adjust the full-scale output current from the nominal 20 mA to as low as 5
mA or as high as 30 mA. The output current can be directly fed to the load with no additional external output
buffer required. The device has been specifically designed for a differential transformer coupled output with a
50-Ω doubly-terminated load.
The DAC5670 is available in a 192-ball CBGA package. The device is characterized for operation over the
military temperature range ( –55°C to 125°C T
case
).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC5670-SP
SGLS386 – JANUARY 2009...............................................................................................................................................................................................
www.ti.com
AVAILABLE OPTIONS
TEMPERATURE
–55°C to 125°C T
case
(1)
PACKAGE
(1)
192-GEM
TOP SIDE SYMBOL
5962-0724701VXA
DAC5670MGEM-V
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
A_ONLY_INV
A_ONLY_ZS
NORMAL
SLEEP
Mode Controls
DA_P[13:0]
100
A_ONLY
CSBIAS
CSBIAS_IN
IOUT_P
DA_N[13:0]
DB_P[13:0]
DB_N[13:0]
DTCLK_P
DTCLK_N
LOCK
RESTART
÷2
INV_CLK
DLYCLK_P
DLYCLK_N
Variable
Delay
Phase
Detector
Loop
Filter
100
100
Input
Registers
Demux
and
Format
14 bit
2.4Gsps
DAC
IOUT_N
RBIASOUT
RBIASIN
REFIO_IN
Bandgap
Ref
REFIO
÷2
LVDS_HTB
DACCLK_P
Figure 1. Functional Block Diagram DAC5670
2
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DAC5670-SP
Copyright © 2009, Texas Instruments Incorporated
DACCLK_N
DAC5670-SP
www.ti.com...............................................................................................................................................................................................
SGLS386 – JANUARY 2009
Table 1. Terminal Assignments (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
DB9_P
DB9_N
DB7_N
DB7_P
DB3_N
DB3_P
DB4_N
DB4_P
DB1_P
DB1_N
DB0_P
DB0_N
2
DB10_N
GND
DB8_P
DB8_N
DB5_N
DB5_P
AVDD
AVDD
DB2_P
DB2_N
AVDD
GND
GND
CSCap
_IN
3
DB10_P
GND
AVDD
DB6_P
AVDD
GND
GND
GND
GND
AVDD
REFIO
AVDD
GND
CSCap
4
DB12_P
DB11_P
AVDD
DB6_N
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
REFIO_I
N
AVDD
AVDD
RBIAS_IN
5
DB12_N
DB11_N
AVDD
AVDD
GND
GND
GND
GND
GND
GND
AVDD
AVDD
GND
RBIAS
_OUT
6
DLYCLK
_N
DB13_N
GND
AVDD
GND
GND
GND
GND
GND
GND
AVDD
IOUT_N
GND
7
DLYCLK
_P
DB13_P
GND
AVDD
GND
GND
AVDD
AVDD
GND
GND
AVDD
IOUT_P
GND
GND
8
DTCLK_N
DA0_P
GND
AVDD
GND
GND
AVDD
AVDD
GND
GND
AVDD
GND
GND
GND
9
DTCLK_P
DA0_N
GND
AVDD
GND
GND
GND
GND
GND
GND
AVDD
GND
GND
LVDS
_htb
10
DA2_N
DA1_P
AVDD
AVDD
GND
GND
GND
GND
GND
GND
AVDD
AVDD
A_only
AVDD
Sleep
A_only
_inv
11
DA2_P
DA1_N
DA7_N
DA6_N
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
GND
GND
12
DA3_N
GND
DA7_P
DA6_P
AVDD
GND
GND
GND
GND
AVDD
Inv_clk
Restart
13
DA3_P
GND
DA5_P
DA5_N
DA9_N
DA9_P
DA11_N
DA11_P
DA13_P
DA13_N
AVDD
GND
A_only_z
M
_Normal
DA4_P
DA4_N
DA8_N
DA8_P
DA10_N
DA10_P
DA12_N
DA12_P
Dacclk_P
Dacclk_N
GND
GND
14
Table 2. Terminal Assignments (Bottom View)
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DB10_N
DB10_P
DB12_P
DB12_N
DLYCLK
_N
DLYCLK
_P
DTCLK_N
DTCLK_P
DA2_N
DA2_P
DA3_N
DA3_P
B
DB9_P
GND
GND
DB11_P
DB11_N
DB13_N
DB13_P
DA0_P
DA0_N
DA1_P
DA1_N
GND
GND
DA4_P
C
DB9_N
DB8_P
AVDD
AVDD
AVDD
GND
GND
GND
GND
AVDD
DA7_N
DA7_P
DA5_P
DA4_N
D
DB7_N
DB8_N
DB6_P
DB6_N
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
DA6_N
DA6_P
DA5_N
DA8_N
E
DB7_P
DB5_N
AVDD
AVDD
GND
GND
GND
GND
GND
GND
AVDD
AVDD
DA9_N
DA8_P
F
DB3_N
DB5_P
GND
AVDD
GND
GND
GND
GND
GND
GND
AVDD
GND
DA9_P
DA10_N
G
DB3_P
AVDD
GND
AVDD
GND
GND
AVDD
AVDD
GND
GND
AVDD
GND
DA11_N
DA10_P
H
DB4_N
AVDD
GND
AVDD
GND
GND
AVDD
AVDD
GND
GND
AVDD
GND
DA11_P
DA12_N
J
DB4_P
DB2_P
GND
AVDD
GND
GND
GND
GND
GND
GND
AVDD
GND
DA13_P
DA12_P
K
DB1_P
DB2_N
AVDD
AVDD
GND
GND
GND
GND
GND
GND
AVDD
AVDD
DA13_N
Dacclk_P
L
DB1_N
AVDD
REFIO
REFIO_I
N
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
GND
Inv_clk
AVDD
Dacclk_N
M
DB0_P
GND
AVDD
AVDD
AVDD
IOUT_N
IOUT_P
GND
GND
AVDD
GND
Restart
GND
GND
A_only_z
GND
N
DB0_N
GND
GND
AVDD
GND
GND
GND
GND
GND
A_only
GND
GND
LVDS_htb
AVDD
Sleep
A_only_in
v
M_Norma
l
CSCap
_IN
CSCap
RBIAS_IN
RBIAS_O
UT
P
Copyright © 2009, Texas Instruments Incorporated
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DAC5670-SP
3
DAC5670-SP
SGLS386 – JANUARY 2009...............................................................................................................................................................................................
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
NAME
DACCLK_P
DACCLK_N
DLYCLK_P
DLYCLK_N
DTCLK_P
DTCLK_N
xxx
BALL NO.
K14
L14
A7
A6
A9
A8
J13
K13
J14
H14
H13
G13
G14
F14
F13
E13
E14
D14
C12
C11
D12
D11
C13
D13
B14
C14
A13
A12
A11
A10
B10
B11
B8
B9
B7
B6
A4
A5
B4
B5
A3
A2
B1
C1
Type
I
I
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
External clock, sample clock for the DAC
Complementary external clock, sample clock for the DAC
DDR type data clock to data source
DDR type data clock to data source complementary signal
Input data toggling reference bit
Input data toggling reference bit, complementary signal
Port A data bit 13 (MSB)
Port A data bit 13 complement (MSB)
Port A data bit 12
Port A data bit 12 complement
Port A data bit 11
Port A data bit 11 complement
Port A data bit 10
Port A data bit 10 complement
Port A data bit 9
Port A data bit 9 complement
Port A data bit 8
Port A data bit 8 complement
Port A data bit 7
Port A data bit 7 complement
Port A data bit 6
Port A data bit 6 complement
Port A data bit 5
Port A data bit 5 complement
Port A data bit 4
Port A data bit 4 complement
Port A data bit 3
Port A data bit 3 complement
Port A data bit 2
Port A data bit 2 complement
Port A data bit 1
Port A data bit 1 complement
Port A data bit 0 (LSB)
Port A data bit 0 complement (LSB)
Port B data bit 13 (MSB)
DA_P[13]
DA_N[13]
DA_P[12]
DA_N[12]
DA_P[11]
DA_N[11]
DA_P[10]
DA_N[10]
DA_P[9]
DA_N[9]
DA_P[8]
DA_N[8]
DA_P[7]
DA_N[7]
DA_P[6]
DA_N[6]
DA_P[5]
DA_N[5]
DA_P[4]
DA_N[4]
DA_P[3]
DA_N[3]
DA_P[2]
DA_N[2]
DA_P[1]
DA_N[1]
DA_P[0]
DA_N[0]
xxx
DB_P[13]
DB_N[13]
DB_P[12]
DB_N[12]
DB_P[11]
DB_N[11]
DB_P[10]
DB_N[10]
DB_P[9]
DB_N[9]
I
I
I
I
I
I
I
I
I
Port B data bit 13 complement (MSB)
Port B data bit 12
Port B data bit 12 complement
Port B data bit 11
Port B data bit 11 complement
Port B data bit 10
Port B data bit 10 complement
Port B data bit 9
Port B data bit 9 complement
4
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Product Folder Link(s):
DAC5670-SP
Copyright © 2009, Texas Instruments Incorporated
DAC5670-SP
www.ti.com...............................................................................................................................................................................................
SGLS386 – JANUARY 2009
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
DB_P[8]
DB_N[8]
DB_P[7]
DB_N[7]
DB_P[6]
DB_N[6]
DB_P[5]
DB_N[5]
DB_P[4]
DB_N[4]
DB_P[3]
DB_N[3]
DB_P[2]
DB_N[2]
DB_P[1]
DB_N[1]
DB_P[0]
DB_N[0]
xxx
BALL NO.
C2
D2
E1
D1
D3
D4
F2
E2
J1
H1
G1
F1
J2
K2
K1
L1
M1
N1
M7
M6
P5
P4
P3
P2
L3
L4
M12
P9
L12
P11
P13
N10
P12
N13
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
I
O
I
O
I
I
I
I
I
I
I
I
I
Port B data bit 8
Port B data bit 8 complement
Port B data bit 7
Port B data bit 7 complement
Port B data bit 6
Port B data bit 6 complement
Port B data bit 5
Port B data bit 5 complement
Port B data bit 4
Port B data bit 4 complement
Port B data bit 3
Port B data bit 3 complement
Port B data bit 2
Port B data bit 2 complement
Port B data bit 1
Port B data bit 1 complement
Port B data bit 0 (LSB)
Port B data bit 0 complement (LSB)
DESCRIPTION
IOUT_P
IOUT_N
xxx
DAC current output. Full scale when all input bits are set 1.
DAC complementary current output. Full scale when all input bits are 0.
Rbias resistor current output
Rbias resistor sense input
Current source bias voltage
Current source bias voltage sense input
Bandgap reference output
Bandgap reference sense input
Resets DLL when high. Low for normal DLL operation.
DLYCLK_P/N control, lvds mode when high, ht mode when low
Inverts the DLL target clocking relationship when high. Low for normal DLL operation.
Active-high sleep
High for {a0,b0,a1,b1,a2,b2, …} normal mode
High for {a0,a0,a1,a1,a2,a2, …} A_only mode
High for {a0,-a0, a1,-a1,a2,-a2, ...} A_only_inv mode
High for {a0,0,a1,0,a2,0, …} A_only_zs mode
RBIASOUT
RBIASIN
CSCAP
CSCAP_IN
REFIO
REFIO_IN
xxx
RESTART
LVDS_HTB
INV_CLK
xxx
SLEEP
NORMAL
A_ONLY
A_ONLY_INV
A_ONLY_ZS
Copyright © 2009, Texas Instruments Incorporated
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Product Folder Link(s):
DAC5670-SP
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