HD151TS302RP
Spread Spectrum Clock for EMI Solution
REJ03D0810-0600
(Previous: ADE-205-655E)
Rev.6.00
Apr 07, 2006
Description
The HD151TS302 is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI solution.
Features
•
•
•
•
•
•
•
Supports 10 MHz to 60 MHz operations. (Designed for XIN = 24 MHz and 48 MHz)
1 copy of clock out with spread spectrum modulation @3.3 V
1 copy of reference clock @3.3 V
Programmable spread spectrum modulation (–0.5%, –1.0%, –3.0% down spread modulation and spread spectrum
disable mode.)
SOP–8pin
Pin to pin compatible with HD151TS301RP
Ordering Information
Part Name
Package Type
SOP-8 pin (JEDEC)
Package Code
(Previous code)
PRSP0008DD-C
(FP-8DCV)
RP
Package
Abbreviation
Taping
Abbreviation (Quantity)
EL (2,500 pcs / Reel)
HD151TS302RPEL
Key Specifications
•
•
•
•
Supply voltages: VDD = 3.3 V±0.165 V
Ta = 0 to 70°C operating range
Clock output duty cycle = 50±5%
Cycle to cycle jitter =
±250
ps typ.
Rev.6.00 Apr 07, 2006 page 1 of 9
HD151TS302RP
Block Diagram
VDD
GND
CLKOUT
XIN
OSC
XOUT
R = 1 MΩ
1/n
SSC Modulator
SEL0
1/m
Synthesizer
SSCCLKOUT
R = 100 kΩ
Mode Control
SEL1
R = 100 kΩ
Pin Arrangement
SSCCLKOUT
1
8
SEL1
VDD
2
7
CLKOUT
GND
3
6
SEL0
XIN
4
5
XOUT
(Top view)
SSC Function Table
SEL1 :0
Spread Percentage
00
–1.0%
01
–3.0%
10
SSC OFF
11
–0.5%
Note: –3.0% SSC is selected for default by internal pull-up & down resistors.
Rev.6.00 Apr 07, 2006 page 2 of 9
HD151TS302RP
Clock Frequency Table
XIN (MHz)
48
24
SSCCLKOUT (MHz)
48
*1
24
*1
CLKOUT (MHz)
48
*2
24
*2
Notes: 1. With spread spectrum modulation.
2. Without spread spectrum modulation.
Pin Descriptions
Pin name
GND
VDD
CLKOUT
SSCCLKOUT
XIN
XOUT
SEL0
SEL1
3
2
7
1
4
5
6
8
No.
Type
Ground
Power
Output
Output
Input
Output
Input
Input
Description
GND pin
Power supplies pin. Normally 3.3 V.
Normally 3.3 V reference clock output.
Spread spectrum modulated clock output.
Oscillator input.
Oscillator output.
SSC mode select pin. LVCMOS level input.
Pull-up by internal resistor. (100 kΩ).
SSC mode select pin. LVCMOS level input.
Pull–down by internal resistor (100 kΩ).
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
*1
Input clamp current
Output clamp current
Continuous output current
Maximum power dissipation
at Ta = 55°C (in still air)
Storage temperature
Notes:
Symbol
VDD
V
I
V
O
I
IK
I
OK
I
O
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to VDD+0.5
–50
–50
±50
0.7
T
stg
–65 to +150
Unit
V
V
V
mA
mA
mA
W
°C
Conditions
V
I
< 0
V
O
< 0
V
O
= 0 to VDD
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
Recommended Operating Conditions
Item
Supply voltage
DC input signal voltage
High level input voltage
Low level input voltage
Operating temperature
Input clock duty cycle
Symbol
VDD
V
IH
V
IL
T
a
Min
3.135
–0.3
2.0
–0.3
0
45
Typ
3.3
—
—
—
—
50
Max
3.465
VDD+0.3
VDD+0.3
0.8
70
55
Unit
V
V
V
V
°C
%
Conditions
Rev.6.00 Apr 07, 2006 page 3 of 9
HD151TS302RP
DC Electrical Characteristics
Ta = 0 to 70°C, VDD = 3.3 V±5%
Item
Input low voltage
Input high voltage
Input current
Symbol
V
IL
V
IH
I
I
Min
—
2.0
—
—
Input slew rate
Input capacitance
Operating current
1
—
—
Typ
—
—
—
—
—
—
7
Max
0.8
—
±10
±100
4
4
—
V / ns
pF
mA
Unit
V
V
µA
Test Conditions
V
I
= 0 V or 3.465 V,
VDD = 3.465 V, XIN pin
V
I
= 0 V or 3.465 V, VDD = 3.465 V,
SEL0, SEL1 pins
20% – 80%
SEL0, SEL1
XIN = 24 MHz, C
L
= 0 pF,
VDD = 3.3 V
C
I
DC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 0 to 70°C, VDD = 3.3 V±5%
Item
Output voltage
Output current *
1
Note:
Symbol
V
OH
V
OL
I
OH
I
OL
Min
3.1
—
—
—
Typ
—
—
–40
40
Max
—
50
—
—
Unit
V
mV
mA
Test Conditions
I
OH
= –1 mA, VDD = 3.3 V
I
OL
= 1 mA, VDD = 3.3 V
V
OH
= 1.5 V
V
OL
= 1.5 V
1. Parameters are target of design. Not 100% tested in production.
Rev.6.00 Apr 07, 2006 page 4 of 9
HD151TS302RP
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25°C, VDD = 3.3 V, C
L
= 30 pF
Item
*1, 2
Cycle to cycle jitter
Symbol
t
CCS
Min
—
—
—
—
—
—
—
Typ
| 250 |
| 250 |
| 250 |
| 250 |
| 250 |
| 250 |
| 250 |
Max
| 300 |
| 300 |
| 300 |
| 300 |
| 300 |
| 300 |
| 300 |
Unit
Test Conditions
SSCCLKOUT,
24 MHz
SSCCLKOUT,
48 MHz
SSCCLKOUT,
24 MHz
SSCCLKOUT,
48 MHz
SSCCLKOUT,
24 MHz
SSCCLKOUT,
48 MHz
CLKOUT,
24 MHz &
48 MHz
SSCCLKOUT,
XIN = 24 MHz
SSCCLKOUT,
XIN = 48 MHz
SSCCLKOUT,
XIN = 24 MHz
SSCCLKOUT,
XIN = 48 MHz
SSCCLKOUT,
XIN = 24 MHz
SSCCLKOUT,
XIN = 48 MHz
CLKOUT,
24 MHz
CLKOUT,
48 MHz
@48 MHz CLKOUT
Notes
SSCOFF
SEL1:0 = 10
Fig1
SSC = –0.5%
SEL1:0 = 11
Figure 1
SSC = –3.0%
SEL1:0 = 01
Figure 1
Figure 1
Output frequency
*1, 2
23.8
47.3
23.7
47.0
23.1
45.9
23.8
47.3
—
—
—
—
—
—
—
—
24.2
48.7
24.2
48.7
24.2
48.7
24.2
48.7
MHz
SSCOFF
SEL1:0 = 10
SSC = –0.5%
SEL1:0 = 11
SSC = –3.0%
SEL1:0 = 01
Slew rate
t
SL
1.0
—
—
V/ns
0.4 V to 2.4 V
*1
Clock duty cycle
45
50
55
%
*1
Output impedance
—
30
—
Ω
—
33
—
KHz
@48 MHz
Spread spectrum
*1
SSCCLKOUT
modulation frequency
Input clock frequency
10
—
60
MHz
*1,3
Stabilization time
—
—
2
ms
Notes: 1. Parameters are target of design. Not 100% tested in production.
2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up.
*1
SSCCLKOUT
(or CLKOUT)
tcycle n
tcycle n+1
t
CCS
= (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.6.00 Apr 07, 2006 page 5 of 9
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