HIP6601A, HIP6603A, HIP6604
TM
Data Sheet
February 2001
File Number
4884.3
Synchronous Rectified Buck MOSFET
Drivers
The HIP6601A, HIP6603A and HIP6604 are high frequency,
dual MOSFET drivers specifically designed to drive two
power N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with a HIP63xx
and the ISL65xx Multi-Phase Buck PWM controller and
Intersil UltraFET® and MOSFETs form a complete core-
voltage regulator solution for advanced microprocessors.
The HIP6601A drives the lower gate in a synchronous
rectifier to 12V, while the upper gate can be independently
driven over a range from 5V to 12V. The HIP6603A drives
both upper and lower gates over a range of 5V to 12V. This
drive-voltage flexibility provides the advantage of optimizing
applications involving trade-offs between switching losses
and conduction losses. The HIP6604 can be configured as
either a HIP6601A or a HIP6603A.
The output drivers in the HIP6601A, HIP6603A and HIP6604
have the capacity to efficiently switch power MOSFETs at
frequencies up to 2MHz. Each driver is capable of driving a
3000pF load with a 30ns propagation delay and 50ns
transition time. These products implement bootstrapping on
the upper gate with only an external capacitor required. This
reduces implementation complexity and allows the use of
higher performance, cost effective, N-Channel MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.
Features
• Drives Two N-Channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Device
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 8 Lead SOIC and EPSOIC and 16 Lead MLFP
Packages
• Dual Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Output Stage Shutdown
• Supply Under Voltage Protection
Applications
• Core Voltage Supplies for Intel Pentium® III, AMD®
Athlon™ Microprocessors
• High Frequency Low Profile DC-DC Converters
• High Current Low Voltage DC-DC Converters
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinouts
HIP6601ACB, HIP6603ACB (SOIC)
HIP6601ECB, HIP6603ECB (EPSOIC)
TOP VIEW
UGATE
BOOT
1
2
3
4
8
7
6
5
PHASE
PVCC
VCC
LGATE
Ordering Information
PART NUMBER
HIP6601ACB
HIP6603ACB
HIP6601ACB-T
HIP6603ACB-T
HIP6601ECB
HIP6603ECB
HIP6601ECB-T
HIP6603ECB-T
HIP6604CR
HIP6604CR-T
TEMP. RANGE
(
o
C)
0 to 85
0 to 85
PACKAGE
8 Ld SOIC
8 Ld SOIC
PKG. NO.
PWM
M8.15
M8.15
GND
8 Ld SOIC Tape and Reel
8 Ld SOIC Tape and Reel
0 to 85
0 to 85
8 Ld EPSOIC
8 Ld EPSOIC
M8.15B
M8.15B
NC
BOOT
PWM
GND
1
2
3
4
HIP6604 (MLFP)
TOP VIEW
PHASE
14
UGATE
NC
NC
13
12 NC
11 PVCC
10 LVCC
9
5
PGND
6
NC
7
LGATE
8
NC
VCC
16
15
8 Ld EPSOIC Tape and Reel
8 Ld EPSOIC Tape and Reel
0 to 85
16 Ld 4x4 MLFP L16.4x4
16 Ld 4x4 MLFP Tape and Reel
Pentium® is a registered trademark of Intel Corporation.
UltraFET® is a registered trademark of Intersil Corporation.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
AMD® is a registered trademark of Advanced Micro Devices, Inc.
|
Athlon™ is a trademark of Advanced Micro Devices, Inc.
HIP6601A, HIP6603A, HIP6604
ti
Block Diagrams
HIP6601A AND HIP6603A
PVCC
VCC
+5V
10K
PWM
10K
BOOT
UGATE
SHOOT-
THROUGH
PROTECTION
PHASE
†
VCC FOR HIP6601A
PVCC FOR HIP6603A
CONTROL
LOGIC
†
LGATE
GND
PAD
FOR HIP6601ECB AND HIP6603ECB DEVICES, THE PAD ON THE BOTTOM
SIDE OF THE PACKAGE MUST BE SOLDERED TO THE PC BOARD.
HIP6604 MLFP PACKAGE
PVCC
VCC
+5V
10K
PWM
CONTROL
LOGIC
10K
GND
PAD
SHOOT-
THROUGH
PROTECTION
BOOT
UGATE
PHASE
CONNECT LVCC TO VCC FOR HIP6601A CONFIGURATION
CONNECT LVCC TO PVCC FOR HIP6603A CONFIGURATION.
LVCC
LGATE
PGND
PAD ON THE BOTTOM SIDE OF THE PACKAGE MUST BE SOLDERED TO THE PC BOARD
2
HIP6601A, HIP6603A, HIP6604
Typical Application - 3 Channel Converter Using HIP6301 and HIP6601A Gate Drivers
+12V
+5V
BOOT
VCC
PWM
PVCC
UGATE
PHASE
DRIVE
HIP6601A
LGATE
+12V
+5V
+5V
BOOT
+V
CORE
VFB
VCC
VSEN
PGOOD
COMP
VCC
PWM1
PWM2
PWM3
PWM
PVCC
UGATE
PHASE
DRIVE
HIP6601A
LGATE
VID
MAIN
CONTROL
HIP6301
ISEN1
ISEN2
FS
GND
ISEN3
+5V
BOOT
PVCC
VCC
PWM
DRIVE
HIP6601A
PHASE
UGATE
+12V
LGATE
3
HIP6601A, HIP6603A, HIP6604
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (V
BOOT
- V
PHASE
). . . . . . . . . . . . . . . . . . . . . . . .15V
Input Voltage (V
PWM
) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE . . . . . . . . . . . . . . . . . . . . . . V
PHASE
- 0.3V to V
BOOT
+ 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
PVCC
+ 0.3V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .200V
Thermal Information
Thermal Resistance
θ
JA
(
o
C/W)
SOIC Package (Note 1) . . . . . . . . . . . . . . . . . . . . . .
97
EPSOIC Package (Note 2). . . . . . . . . . . . . . . . . . . .
38
MLFP Package (Note 2). . . . . . . . . . . . . . . . . . . . . .
43
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0
o
C to 85
o
C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125
o
C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
Upper Gate Bias Current
POWER-ON RESET
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT
Input Current
PWM Rising Threshold
PWM Falling Threshold
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
I
VCC
I
PVCC
TEST CONDITIONS
HIP6601A, f
PWM
= 1MHz, V
PVCC
= 12V
HIP6603A, f
PWM
= 1MHz, V
PVCC
= 12V
HIP6601A, f
PWM
= 1MHz, V
PVCC
= 12V
HIP6603A, f
PWM
= 1MHz, V
PVCC
= 12V
MIN
-
-
-
-
9.7
9.0
I
PWM
V
PWM
= 0 or 5V (See Block Diagram)
-
3.45
-
t
RUGATE
t
RLGATE
t
FUGATE
t
FLGATE
t
PDLUGATE
t
PDLLGATE
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
-
-
-
-
-
-
1.4
-
R
UGATE
R
UGATE
I
LGATE
V
PVCC
= 5V
V
PVCC
= 12V
V
PVCC
= 5V
V
PVCC
= 12V
V
PVCC
= 5V, HIP6603A
V
PVCC
= 12V, HIP6603A
V
PVCC
= 5V or 12V, HIP6601A
-
-
-
-
400
500
500
-
TYP
4.4
2.5
200
1.8
9.95
9.2
500
3.6
1.45
20
50
20
20
30
20
-
230
1.7
3.0
2.3
1.1
580
730
730
1.6
MAX
6.2
3.6
430
3.3
10.4
9.5
-
-
1.55
-
-
-
-
-
-
3.6
-
3.0
5.0
4.0
2.0
-
-
-
4.0
UNITS
mA
mA
µA
mA
V
V
µA
V
V
ns
ns
ns
ns
ns
ns
V
ns
Ω
Ω
Ω
Ω
mA
mA
mA
Ω
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
Shutdown Window
Shutdown Holdoff Time
OUTPUT
Upper Drive Source Impedance
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Sink Impedance
R
LGATE
V
PVCC
= 5V or 12V
4
HIP6601A, HIP6603A, HIP6604
Functional Pin Description
UGATE (Pin 1), (Pin 16 MLFP)
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
PVCC (Pin 7), (Pin 11 MLFP)
For the HIP6601A and the HIP6604, this pin supplies the
upper gate drive bias. Connect this pin from +12V down to
+5V.
For the HIP6603A, this pin supplies both the upper and
lower gate drive bias. Connect this pin to either +12V or +5V.
BOOT (Pin 2), (Pin 2 MLFP)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PHASE (Pin 8), (Pin 14 MLFP)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. The PHASE voltage is
monitored for adaptive shoot-through protection. This pin
also provides a return path for the upper gate drive.
PWM (Pin 3), (Pin 3 MLFP)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
Description
Operation
Designed for versatility and speed, the HIP6601A, HIP6603A
and HIP6604 dual MOSFET drivers control both high-side and
low-side N-Channel FETs from one externally provided PWM
signal.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [t
PDLLGATE
], the
lower gate begins to fall. Typical fall times [t
FLGATE
] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [t
PDHUGATE
] based
on how quickly the LGATE voltage drops below 2.2V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[t
RUGATE
] and the upper MOSFET turns on.
GND (Pin 4), (Pin 4 MLFP)
Bias and reference ground. All signals are referenced to this
node.
PGND (Pin 5 MLFP Package Only)
This pin is the power ground return for the lower gate driver.
LGATE (Pin 5), (Pin 7 MLFP)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6), (Pin 9 MLFP)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND.
LVCC (Pin 10 MLFP Package Only)
Lower gate driver supply voltage.
Timing Diagram
PWM
t
PDHUGATE
t
PDLUGATE
t
RUGATE
t
FUGATE
UGATE
LGATE
t
FLGATE
t
PDLLGATE
t
PDHLGATE
t
RLGATE
5
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