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D2
PA
K
BUK7618-55
N-channel TrenchMOS standard level FET
Rev. 2 — 26 April 2011
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
AEC Q101 compliant
Electrostatically robust due to
integrated protection diodes
Low conduction losses due to low
on-state resistance
1.3 Applications
Automotive and general purpose
power switching
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
non-repetitive
drain-source
avalanche energy
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C
I
D
= 50 A; V
sup
≤
25 V;
R
GS
= 50
Ω;
V
GS
= 10 V;
T
j(init)
= 25 °C; unclamped
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
mb
= 25 °C
Min Typ Max Unit
-
-
-
-
-
-
-
15
55
57
V
A
125 W
18
mΩ
Static characteristics
Avalanche ruggedness
E
DS(AL)S
-
-
125 mJ
NXP Semiconductors
BUK7618-55
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base;
connected to drain
2
1
3
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
SOT404 (D2PAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK7618-55
D2PAK
Description
plastic single-ended surface-mounted package (D2PAK);
3 leads (one lead cropped)
Version
SOT404
Type number
BUK7618-55
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 April 2011
2 of 12
NXP Semiconductors
BUK7618-55
N-channel TrenchMOS standard level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
electrostatic discharge voltage
T
mb
= 25 °C
pulsed; T
mb
= 25 °C
I
D
= 50 A; V
sup
≤
25 V; R
GS
= 50
Ω;
V
GS
= 10 V; T
j(init)
= 25 °C; unclamped
HBM; C = 100 pF; R = 1.5 kΩ; (all pins)
T
mb
= 25 °C
T
mb
= 100 °C
T
mb
= 25 °C; pulsed
T
mb
= 25 °C
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
Min
-
-
-16
-
-
-
-
-55
-55
-
-
-
Max
55
55
16
57
40
228
125
175
175
57
200
125
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
Electrostatic discharge
V
esd
-
2
kV
100
P
der
(%)
80
003aaf190
100
I
D
(%)
80
003aaf191
60
60
40
40
20
20
0
0
40
80
120
160
200
T
mb
(°C)
0
0
40
80
120
160
200
T
mb
(°C)
V
GS
≥
5 V
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig 2.
Normalized continuous drain current as a
function of mounting base temperature
BUK7618-55
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 April 2011
3 of 12
NXP Semiconductors
BUK7618-55
N-channel TrenchMOS standard level FET
10
3
I
DM
(A)
10
2
R
DS(on)
= V
DS
/ I
D
003aaf192
120
WDSS
(%)
80
003aaf204
t
p
= 1
μs
10
μs
100
μs
10
D.C.
1 ms
10 ms
100 ms
40
1
1
10
V
DS
(V)
10
2
0
20
60
100
140
180
T
(mb)
(°C)
T
mb
= 25 °C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
Fig 4.
I
D
= 75 A
Normalised drain-source avalanche energy as a
function of mounting-base temperature.
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to mounting base
thermal resistance from
junction to ambient
minimum footprint; FR4 board
Conditions
Min
-
-
Typ
-
50
Max
1.2
-
Unit
K/W
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
−1
0.1
0.05
0.02
0
t
p
P
003aaf193
δ
=
t
p
T
10
−2
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
1
10
t
p
(s)
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK7618-55
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 April 2011
4 of 12
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