HD74ALVCH162835
18-bit Universal Bus Drivers with 3-state Outputs
ADE-205-189B (Z)
3rd. Edition
December 1999
Description
Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent
mode when LE is high. The A data is latched if CLK is held at a high or low logic level. If LE is low, the
A bus data is stored in the latch flip flop on the low to high transition of CLK. When
OE
is high, the
outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating
data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26
Ω
resistors to reduce overshoot and undershoot.
Features
•
V
CC
= 2.3 V to 3.6 V
•
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
•
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
•
High output current
±12
mA (@V
CC
= 3.0 V)
•
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
•
All outputs have equivalent 26
Ω
series resistors, so no external resistors are required.
HD74ALVCH162835
Function Table
Inputs
OE
H
L
L
L
L
L
L
LE
X
H
H
L
L
L
L
CLK
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
Z
L
H
L
H
Y
0
Y
0
*1
*2
Output Y
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑
: Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established, provided that
CLK is high before LE goes low.
2. Output level before the indicated steady state input conditions were established.
2
HD74ALVCH162835
Pin Arrangement
NC 1
NC 2
Y1 3
GND 4
Y2 5
Y3 6
V
CC
7
Y4 8
Y5 9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
V
CC
22
Y16 23
Y17 24
GND 25
Y18 26
OE
27
LE 28
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 V
CC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 V
CC
34 A16
33 A17
32 GND
31 A18
30 CLK
29 GND
(Top view)
3
HD74ALVCH162835
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1
Output voltage
*1, 2
Input clamp current
Output clamp current
Continuous output current
V
CC
, GND current / pin
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature
Notes:
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
CC
+0.5
–50
±50
±50
±100
1
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
W
°C
TSSOP
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
High level output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.3
0
0
—
—
—
Low level output current
I
OL
—
—
—
Input transition rise or fall rate
Operating temperature
∆t
/
∆v
Ta
0
–40
Max
3.6
V
CC
V
CC
–6
–8
–12
6
8
12
10
85
ns / V
°C
mA
Unit
V
V
V
mA
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
4
HD74ALVCH162835
Logic Diagram
OE
CLK
LE
A1
27
30
28
54
1D
C1
CLK
3
Y1
To seventeen other channels
5
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