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CY7C243-20WC

产品描述UVPROM, 4KX8, 20ns, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24
产品类别存储    存储   
文件大小756KB,共11页
制造商Cypress(赛普拉斯)
下载文档 详细参数 全文预览

CY7C243-20WC概述

UVPROM, 4KX8, 20ns, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24

CY7C243-20WC规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Cypress(赛普拉斯)
零件包装代码DIP
包装说明0.300 INCH, WINDOWED, CERDIP-24
针数24
Reach Compliance Codenot_compliant
ECCN代码EAR99
最长访问时间20 ns
I/O 类型COMMON
JESD-30 代码R-GDIP-T24
JESD-609代码e0
内存密度32768 bit
内存集成电路类型UVPROM
内存宽度8
功能数量1
端子数量24
字数4096 words
字数代码4000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织4KX8
输出特性3-STATE
封装主体材料CERAMIC, GLASS-SEALED
封装代码DIP
封装等效代码DIP24,.3
封装形状RECTANGULAR
封装形式IN-LINE
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
认证状态Not Qualified
最大压摆率0.1 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
Base Number Matches1

文档预览

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CY7C243
4K x 8 Reprogrammable PROM
Features
CY7C244
D
D
D
Capable of withstanding greater than
2001V static discharge
D
D
D
CMOS for optimum speed/power
Windowed for reprogrammability
High speed
20 ns (commercial)
25 ns (military)
TTL compatible I/O
Direct replacement for bipolar
PROMs
Functional Description
D
Low power
550 mW (commercial)
660 mW (military)
D
D
D
EPROM technology 100% program
mable
300 mil or 600 mil packaging avail
able
5V ± 10% V
CC
, commercial and
military
The CY7C243 and CY7C244 are high
performance 4K x 8 CMOS PROMs. The
CY7C243 and CY7C244 are packaged in
300 mil wide and 600 mil wide packages
respectively. The reprogrammable pack
ages are equipped with an erasure win
dow. When exposed to UV light, these
PROMs are erased and can then be repro
grammed. The memory cells utilize prov
en EPROM floating gate technology and
byte wide intelligent programming algo
rithms.
The CY7C243 and CY7C244 are plug in
replacements for bipolar devices and offer
the advantages of lower power, superior
performance and programming yield. The
EPROM cell requires only 12.5V for the
supervoltage and low current require
ments allow for gang programming. The
EPROM cells allow for each memory lo
cation to be tested 100%, as each cell is
programmed, erased, and repeatedly exer
cised prior to encapsulation. Each PROM
is also tested for AC performance to guar
antee that after customer programming
the product will meet DC and AC specifi
cation limits.
Read is accomplished by placing an active
LOW signal on CS
1
and an active HIGH
on CS
2
. The contents of the memory loca
tion addressed by the address line (A
0
-
A
11
) will become available on the output
lines (O
0
- O
7
).
DIP/Flatpack
Top View
Logic Block Diagram
Pin Configurations
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
O
7
ROW
ADDRESS
PROGRAM
MABLE
ARRAY
COLUMN
MULTI
PLEXER
O
6
O
5
ADDRESS
DECODER
COLUMN
ADDRESS
O
4
O
3
O
2
O
1
O
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
24
2
23
3
22
4
21
5
20
6
19
18
7
8 7C243 17
9 7C244 16
10
15
14
11
12
13
V
CC
A
8
A
9
A
10
CS
1
A
11
CS
2
O
7
O
6
O
5
O
4
O
3
C243-2
LCC/PLCC (Opaque Only)
Top View
CS
1
CS
2
C243-1
A
4
A
3
A
2
A
1
A
0
NC
O
0
4 3 2 1 28 27 26
25
5
7C243 24
6
23
7
22
8
21
9
20
10
19
1112 13 14 151617 18
O1
O2
GND
NC
O3
O4
O5
A5
A6
A7
NC
VCC
A8
A9
A
10
CS
1
A
11
CS
2
NC
O
7
O
6
C243-3
7C243-35
7C244-35
7C243-45
7C244-45
7C243-55
7C244-55
Selection Guide
7C243-20
7C243-25
7C244-25
Maximum Access Time (ns)
Commercial
Maximum Operating
Current (mA)
Military
Cypress Semiconductor Corporation
7C244-20
20
100
25
100
120
35
80
100
45
80
100
55
80
100
D
3901 North First Street
1
D
San Jose
D
CA 95134
D
408-943-2600
May 1994 - Revised August 1994

 
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