H8/3067 Series
H8/3067, H8/3066, H8/3065
H8/3067 F-ZTAT
H8/3067F, H8/3067FR
Hardware Manual
TM
ADE-602-135B
Rev. 3.0
22/2/99
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8/3067 Series is a series of high-performance single-chip microcontrollers that integrate
system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a DMA controller (DMAC), and
other facilities. The three-channel SCI has been expanded to support the ISO/IEC7816-3 smart
card interface. Functions have also been added to reduce power consumption in battery-powered
applications: individual modules can be placed in standby, and the frequency of the system clock
supplied to the chip can be divided down under software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3067 Series offers easy implementation of compact, high-performance
systems.
In addition to its mask ROM versions, the H8/3067 Series has an F-ZTAT™* version with on-
chip flash memory that can be programmed on-board. This version enables users to respond
quickly and flexibly to changing application specifications.
This manual describes the H8/3067 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Note: * F-ZTAT™ (Flexible ZTAT) is a registered trademark of Hitachi, Ltd.
Contents
Section 1
1.1
1.2
1.3
Overview
...........................................................................................................
1.4
Overview............................................................................................................................
Block Diagram...................................................................................................................
Pin Description ..................................................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1.3.2 Pin Functions........................................................................................................
1.3.3 Pin Assignments in Each Mode............................................................................
Notes on Flash Memory R Version Model........................................................................
1.4.1 Pin Arrangement ..................................................................................................
1.4.2 Product Type Names and Markings .....................................................................
1.4.3 Differences in Flash Memory R Version..............................................................
1
1
6
7
7
9
14
18
18
18
19
Section 2
2.1
CPU
..................................................................................................................... 21
21
21
22
23
24
25
25
26
27
28
29
29
30
32
32
33
34
43
45
47
47
49
53
53
54
54
i
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview............................................................................................................................
2.1.1 Features ................................................................................................................
2.1.2 Differences from H8/300 CPU.............................................................................
CPU Operating Modes ......................................................................................................
Address Space....................................................................................................................
Register Configuration ......................................................................................................
2.4.1 Overview ..............................................................................................................
2.4.2 General Registers..................................................................................................
2.4.3 Control Registers..................................................................................................
2.4.4 Initial CPU Register Values .................................................................................
Data Formats......................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats..........................................................................................
Instruction Set....................................................................................................................
2.6.1 Instruction Set Overview......................................................................................
2.6.2 Instructions and Addressing Modes .....................................................................
2.6.3 Tables of Instructions Classified by Function......................................................
2.6.4 Basic Instruction Formats.....................................................................................
2.6.5 Notes on Use of Bit Manipulation Instructions....................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Addressing Modes................................................................................................
2.7.2 Effective Address Calculation..............................................................................
Processing States ...............................................................................................................
2.8.1 Overview ..............................................................................................................
2.8.2 Program Execution State ......................................................................................
2.8.3 Exception-Handling State ....................................................................................
2.9
2.8.4 Exception-Handling Sequences............................................................................
2.8.5 Bus-Released State ...............................................................................................
2.8.6 Reset State ............................................................................................................
2.8.7 Power-Down State................................................................................................
Basic Operational Timing..................................................................................................
2.9.1 Overview ..............................................................................................................
2.9.2 On-Chip Memory Access Timing ........................................................................
2.9.3 On-Chip Supporting Module Access Timing.......................................................
2.9.4 Access to External Address Space .......................................................................
56
57
57
57
58
58
58
59
60
Section 3
3.1
MCU Operating Modes
................................................................................ 61
3.2
3.3
3.4
3.5
3.6
Overview............................................................................................................................ 61
3.1.1 Operating Mode Selection.................................................................................... 61
3.1.2 Register Configuration ......................................................................................... 62
Mode Control Register (MDCR) ....................................................................................... 63
System Control Register (SYSCR).................................................................................... 64
Operating Mode Descriptions............................................................................................ 66
3.4.1 Mode 1.................................................................................................................. 66
3.4.2 Mode 2.................................................................................................................. 66
3.4.3 Mode 3.................................................................................................................. 66
3.4.4 Mode 4.................................................................................................................. 67
3.4.5 Mode 5.................................................................................................................. 67
3.4.6 Mode 6.................................................................................................................. 67
3.4.7 Mode 7.................................................................................................................. 67
Pin Functions in Each Operating Mode............................................................................. 68
Memory Map in Each Operating Mode............................................................................. 68
3.6.1 Note on Reserved Areas ....................................................................................... 68
Section 4
4.1
Exception Handling
........................................................................................ 75
75
75
75
76
78
78
78
81
82
83
84
85
4.2
4.3
4.4
4.5
4.6
Overview............................................................................................................................
4.1.1 Exception Handling Types and Priority ...............................................................
4.1.2 Exception Handling Operation .............................................................................
4.1.3 Exception Vector Table........................................................................................
Reset ..................................................................................................................................
4.2.1 Overview ..............................................................................................................
4.2.2 Reset Sequence.....................................................................................................
4.2.3 Interrupts after Reset ............................................................................................
Interrupts............................................................................................................................
Trap Instruction .................................................................................................................
Stack Status after Exception Handling ..............................................................................
Notes on Stack Usage........................................................................................................
ii
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
