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Superscalar IEEE Floating-Point-Processor
Off-Chip Harvard Architecture Maximizes Signal Processing Performance
50 ns, 20 MIPS Instruction Rate, Single Cycle Execution
60 MFLOPS Peak, 40 MFLOPS Sustained Performance
1024-Point Complex FFT Benchmark: 0.975 ms
Divide (y/x): 300 ns
Inverse Square Root (1/ /x): 450 ns
32-bit Single-Precision and 40-bit Extended-Precision IEEE Floating-Point Data
Formats
32-bit Fixed-Point Formats, Integer and Fractional, with 80-bit Accumulators
IEEE Exception Handling with Interrupt on Exception
Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter
Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse
Addressing Modes
Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle
Multiply and ALU Operations
Multiply with Add and Subtract for FFT Butterfly Computation
Efficient Program Sequencing with Zero Overhead Looping: Single-Cycle Loop Setup
Single-Cycle Register File Context Switch
23ns External RAM Access Time for Zero-Wait-State, 40 ns Instruction Execution
IEEE JTAG Standard 1149.1 Test Access Port and On-chip Emulation Circuitry
223 CPGA package for breadboarding
256 Multi-layer Quad Flat Pack, Flat Leads, For Flight Models
Fully compatible with Analog Devices ADSP-21020
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm
2
Tested up to a Total Dose of 100 krads (Si) according to MIL STD 883 Method 1019
SEU Error Note in GEO Orbit Better than 5E
-7
Error/Device/Day (worst case)
For 25 MHz Specification, Contact Atmel for Availability
Quality Grades - ESCC with 9512/002 and QML-Q or V with 5962-99539
Rad. Hard
32/40-bit IEEE
Floating Point
DSP
TSC21020F
Introduction
Atmel is manufacturing a radiation hard version of the Analog Devices ADSP-21020
32/40-bit Floating-Point DSP.
The product is pin and code compatible with ADI product, making system develop-
ment straight forward and cost effective, using existing development tools and
algorithms.
Notes:
1. Design using patent from INPG-CNRS Denis BESSOT/Raoul VELAZCO
2. Product licensed from Analog Devices Inc.
Rev. 4153I-AERO–04/07
1
Functional Block Diagram
2
TSC21020F
4153H–AERO–04/07
TSC21020F
General Description
The TSC21020F is single-chip IEEE floating-point processor optimized for digital signal
processing applications
(1)
. Its architecture is similar to that of Analog Devices' ADSP-
2100 family of fixed-point DSP processors.
Fabricated in a high-speed, low-power and radiation hard CMOS process, the
TSC21020F has a 50ns instruction cycle time. With a high-performance On-chip instruc-
tion cache, the TSC21020F can execute every instruction in a single cycle.
The TSC21020F features:
Independent Parallel
Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions.
The units are architecturally arranged in parallel, maximizing computational throughput.
A single multifunction instruction executes parallel ALU and multiplier operations. These
computation units support IEEE 32-bit single-precision floating-point, extended preci-
sion 40-bit floating-point, and 32-bit fixed-point data formats.
A general-purpose data register file is used for transferring data between the computa-
tion units and the data buses, and for storing intermediate results. This 10-port (16-
register) register file, combined with the TSC21020F's Harvard architecture, allows
unconstrained data flow between computation units and off-chip memory.
The TSC21020F uses a modified Harvard architecture in which data memory stores
data and program memory stores both instructions and data. Because of its separate
program and data memory buses and On-chip instruction cache, the processor can
simultaneously fetch an operand from data memory, an operand from program memory,
and an instruction from the cache, all in a single cycle.
Addressing of external memory devices by the TSC21020F is facilitated by On-chip
decoding of high-order address lines to generate memory bank select signals. Separate
control lines are also generated for simplified addressing of page-mode DRAM. The
TSC21020F provides programmable memory wait states, and external memory
acknowledge controls allow interfacing to peripheral devices with variable access times.
The TSC21020F includes a high performance instruction cache that enables three-bus
operation for fetching an instruction and two data values. The cache is selective-only the
instructions whose fetches conflict with program memory data accesses are cached.
This allows full-speed execution of core, looped operations such as digital filter multiply-
accumulates and FFT butterfly processing.
The TSC21020F provides hardware to implement circular buffers in memory, which are
common in digital filters and Fourier transform implementations. It handles address
pointer wraparound, reducing overhead (thereby increasing performance) and simplify-
ing implementation. Circular buffers can start and end at any location.
The TSC21020F's 48-bit instruction word accommodates a variety of parallel opera-
tions, for concise programming. For example, the TSC21020F can conditionally execute
a multiply, an add, a subtract and a branch in a single instruction.
Data Register File
Single-Cycle Fetch of
Instruction and Two
Operands
Memory Interface
Instruction Cache
Hardware Circular
Buffers
Flexible Instruction Set
1.
It is fully compatible with Analog Devices ADSP-21020
3
4153H–AERO–04/07
Development System
The TSC21020F is supported with a complete set of software and hardware develop-
ment tools from Analog Devices. The ADSP-21000 Family Development System from
Analog Devices includes development software, an evaluation board and an in-circuit
emulator.
Creates relocatable, COFF (Common Object File Format) object files from ADSP-21xxx
assembly source code. It accepts standard C preprocessor directives for conditional
assembly and macro processing. The algebraic syntax of the ADSP-21xxx assembly
language facilitates coding and debugging of DSP algorithms.
The Linker processes separately assembled object files and library files to create a sin-
gle executable program. It assigns memory locations to code and to data in accordance
with a user-defined architecture file that describes the memory and I/O configuration of
the target system. The Librarian allows you to group frequently used object files into a
single library file that can be linked with your main program.
The Simulator performs interactive, instruction-level simulation of ADSP-21xxx code
within the hardware configuration described by a system architecture file. It flags illegal
operations and supports full symbolic disassembly. It provides an easy-to-use, window
oriented, graphical user interface that is identical to the one used by the ADSP- 21020
EZ-ICE Emulator. Commands are accessed from pull-down menus with a mouse.
Formats an executable file into files that can be used with an industry-standard PROM
programmer.
The C Compiler complies with ANSI specifications. It takes advantage of the
TSC21020F's high-level language architectural features and incorporates optimizing
algorithms to speed up the execution of code. It includes an extensive runtime library
with over 100 standard and DSP-specific functions.
A full-featured C source level debugger that works with the simulator or EZ-ICE emula-
tor to allow debugging of assembler source, C source, or mixed assembler and C.
Supports ANSI Standard (X3J11.1) Numerical C as defined by the Numeric C Exten-
sions Group. The compiler accepts C source input containing Numerical C extensions
for array selection, vector math operations, complex data types, circular pointers, and
variably dimensioned arrays, and outputs ADSP-21xxx assembly language source
code.
The EZ-LAB Evaluation Board is a general-purpose, standalone TSC21020F system
that includes 32K words of program memory and 32K words of data memory as well as
analog I/O. A PC RS-232 download path enables the user to download and run pro-
grams directly on the EZ-LAB. In addition, it may be used in conjunction with the EZ-ICE
Emulator to provide a powerful software debug environment.
This in-circuit emulator provides the system designer with a PC-based development
environment that allows non-intrusive access to the TSC21020F's internal registers
through the processor's 5-pin JTAG Test Access Port. This use of On-chip emulation
circuitry enables reliable, full-speed performance in any target. The emulator uses the
same graphical user interface as the ADSP- 21020 Simulator, allowing an easy transi-
Assembler
Linker/Librarian
Simulator
PROM Splitter
C Compiler and Runtime
Library
C Source Level
Debugger
Numerical C Compiler
ADSP- 21020 EZ-LAB
®
Evaluation Board
ADSP- 21020 EZ-ICE
®
Emulator
4
TSC21020F
4153H–AERO–04/07
TSC21020F
tion from software to hardware debug. (See "Target System Requirements for Use of
EZ-ICE Emulator" on page 27.)
®
EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc.
Additional Information
This data sheet provides a general overview of TSC21020F functionality. For additional
information on the architecture and instruction set of the processor, refer to the ADSP-
21020 User's Manual. For development system and programming reference informa-
tion, refer to the ADSP-21000 Family Development Software Manuals and the ADSP-
21020 Programmer's Quick Reference.
5
4153H–AERO–04/07
FPGA/CPLD
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