Si501/2/3/4
LVCMOS CMEMS Programmable Oscillator Series
Description
The Si501/2/3/4 CMEMS programmable oscillator series combines
standard CMOS + MEMS in a single, monolithic IC to provide high-quality
and high-reliability oscillators. Each device is specified for guaranteed
performance across voltage, process, temperature, shock, vibration and
aging for 10 years. More information on CMEMS available at
www.silabs.com/cmems.
Applications:
General purpose microcontrollers, industrial control, IP
cameras, surveillance systems, metering, home and office automation,
security systems, sleep clocking, 10/100 Ethernet/EtherCAT, SPI, SAS3.0 /
SATA3.0, PCIe ref clock, NVMe, HDD, SSD, hybrid storage, DDR3/3L,
USB2.0, USB OTG/2.0, M2M, HDMI
Not recommended:
Wi-Fi, Bluetooth, USB 3.0, Gigabit Ethernet
®
Features
Any frequency oscillator from 32 kHz to 100 MHz
o
Contact Silicon Labs Marketing for frequencies above
100 MHz
Frequency stability: ±20/±30/±50 ppm including 10-year
aging
-20 to +70 °C: Extended Commercial
-40 to +85 °C: Industrial
Highly configurable: low power vs. low jitter, frequency, F
STAB
,
T
R
/T
F
, V
DD
, OE/FS functionality (see ordering guide below)
In-circuit programmable via C1D 1-pin interface (Si504)
Seamless V
DD
from +1.71 to +3.63 V
Low period jitter mode / low power mode
Glitchless start and stop
RoHS compliant, Pb-free
Product Selector Guide
Part
Number
Si501
Si502
Si503
Si504
Description
Single frequency
Dual frequency
Quad frequency
Programmable for any
supported frequency
or configuration
Control
OE
FS/OE
FS
C1D 1-pin interface
(see Si504 data sheet
for details)
Pin-out
Pin 4
VDD
Pin 3
CLK
Pin Description
Pin
Number
1
Description
FS = Frequency Select
OE = Output Enable
C1D = Single wire interface
GND = Ground
CLK = Clock out
VDD = Power Supply
Pin 1
FS/OE/C1D
Pin 2
GND
(top view)
2
3
4
Ordering Guide
VDD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1.7-3.6
3.3V
2.5V
1.8V
1.7-3.6
1.7-3.6
1.7-3.6
1.7-3.6
3.3V
2.5V
1.8V
1.7-3.6
1.7-3.6
1.7-3.6
TYP
Jitter vs
T
R
/T
F
Power
0.7 ns
1
1.3 ns
2
1.3 ns
2
Low
1.3 ns
2
Power
3 ns
3
5 ns
3
8 ns
3
0.7 ns
1
1.3 ns
2
1.3 ns
2
1.3 ns
2
Low Jitter
3 ns
3
5 ns
3
8 ns
3
Description
Single frequency
Dual frequency
Quad frequency
Any frequency
501
OE
OE
Internal
High
Low Pull Resistor
Stop
Enable Doze
Pull-Up
Sleep
Stop
Doze Enable Pull-Down
Sleep
Stop
Enable Doze
Sleep
None
Stop
Doze Enable
Sleep
502
6
OE
Low
Stop
Doze
Sleep
Stop
Doze
Sleep
Internal
Pull Resistor
Pull-Up
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
A
B
None
504 only
5
Maximum F
OUT
A
B
0.032 – 80 MHz
0.032 – 100 MHz
Temp
Range
F
-20 to 70 °C
G
-40 to 85 °C
503
Pull-Up
None
504
Pull-Up only
A
OPN
Prefix
501
502
503
504
50X
-
-
-
-
-
-
-
-
-
-
- A - R
Reel
R
Reel
Cut Tape
Package
Dimension
3.2 x 5 mm
4
2.5 x 3.2 mm
2 x 2.5 mm
ppm
A
B
C
± 50
± 30
± 20
Freq
OPN
Description
Code
Mxxxxxx
f
OUT
< 1 MHz
xMxxxxx
1 MHz ≤ f
OUT
< 10 MHz
501 only
xxMxxxx
10 MHz ≤ f
OUT
< 100 MHz
100M000
f
OUT
= 100 MHz
501/2/3/4 xxxxxx
Silicon Labs 6-digit code for 502/3/4, or >6-decimal freq on 501
B
C
D
Ordering Guide Notes:
1. Series termination resistor (R
S
– see Apps Circuits section) is recommended for this configuration.
2. Series termination resistor (R
S
) is not needed for this configuration. Output impedance is 50Ω for the indicated supply condition.
3. Series termination resistor (R
S
) is not needed for this configuration. Reduced EMI setting.
4. 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm footprint.
5. Select option to support maximum anticipated frequency needed.
Revision 0.72
www.silabs.com/cmems
Copyright© 2013 by Silicon Labs
Si501/2/3/4 CMEMS Oscillator Series
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si501/2/3/4
LVCMOS CMEMS Programmable Oscillator Series
6. The Si502 OE pin has three (3) states: OE High = Freq 1; OE Weak High = Freq 2; OE Low is configurable.
®
Selected Electrical Specifications
V
DD
= +1.71 V to +3.63 V, T
A
= -40 to 85 ºC unless stated otherwise.
Parameter
Frequency Range
Supply Voltage
Supply Current
Symbol
F
CLK
V
DD
I
DD1
Static Supply Current
1
I
DD2
Test Condition/Comment
Programmable family range
Supports continuous V
DD
from Min to Max
3.3 V
DD
, F
CLK
= 1 MHz, 4 pF, Low Power mode
3.3 V
DD
, F
CLK
= 1 MHz, 4 pF, Low Jitter mode
Stop mode, F
CLK
= 1 MHz, Low Power mode
Stop mode, F
CLK
= 1 MHz, Low Jitter mode
Doze mode
Sleep mode
TA = -20 ºC to +70 ºC, -40 ºC to +85 ºC
1
st
option code = A
4
or H
4
1
st
option code = B, C, D, J, K, L
1
st
option code = E, M
1
st
option code = F, N
1
st
option code = G, P
F
CLK
= 100 MHz, Low Jitter mode
1
st
option code = H
F
CLK
= 100 MHz, Low Jitter mode
1
st
option code = H
F
CLK
= 100 MHz, Low Jitter mode
1
st
option code = H
F
CLK
= 75 MHz, F
OFFSET
= 900 kHz - 7.5 MHz
Low Jitter mode, 1
st
option code = H
Drive strength selected such that T
R
/T
F
(20% to 80%) < 10 % of period
Frequency Stability
2
F
STAB
CMOS Rise/Fall Time
3
T
R
/T
F
Min
0.032
1.71
—
—
—
—
—
—
-20
-30
-50
0.4
1
2
4
7
—
—
—
—
45
Typ
—
—
1.7
3.9
1.7
3.9
670
0.3
—
—
—
0.7
1.3
3
5
8
14
9
1
1
50
Max
100
3.63
2.5
4.9
2.5
4.9
890
1
+20
+30
+50
1.2
1.6
4
7
11
25
13
1.6
1.3
55
Unit
MHz
V
mA
mA
mA
mA
A
A
ppm
ppm
ppm
ns
ns
ns
ns
ns
ps pk-pk
ps pk-pk
ps rms
ps rms
%
Cycle-to-Cycle Jitter
Period Jitter Pk-Pk
Period Jitter
Phase Jitter
5
Duty Cycle
J
CCPP
J
PPKPK
J
PRMS
DC
Input High Voltage
V
IH
0.7 x V
DD
—
—
V
Input Low Voltage
V
IL
—
—
0.3 x V
DD
V
Output High Voltage
V
OH
0.9 x V
DD
—
—
V
Output Low Voltage
V
OL
—
—
0.1 x V
DD
V
1. Si501 supports OE/mode functionality. Si502 supports OE/mode and FS functionality. Si503 supports only FS functionality. See data
sheet functional description section for more information.
2. Frequency stability includes initial tolerance, solder shift, operating temp range, rated power supply voltage change, load change, 10-year
aging, shock, and vibration.
3. C
L
= 15 pF, T
R
/T
F
(20% to 80%), 3.3 V unless otherwise stated. See datasheet for additional T
R
/T
F
options.
4. Recommended series termination resistor (R
S
) = 24.9
for Z
0
=50
.
5. Integrated phase jitter exceeds some high-performance data communications system requirements. See AN783 for more information.
Absolute Maximum Ratings
1
Condition
Parameter
Symbol
Rating
Unit
Storage Temperature
T
S
-55 to 125
ºC
Supply Voltage
V
DD
-0.5 to 3.8
ºC
Input Voltage
V
IN
0.5 to V
DD
+0.3
V
ESD HBM (JESD22-A114)
HBM
2000
V
ESD CDM
CDM
500
V
Solder Temp
2
T
PEAK
260
ºC
Solder Time at T
PEAK2
T
P
20-40
s
Max Junction Temp
T
J
125
ºC
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not
implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
2
Revision 0.72
www.silabs.com/cmems
Si501/2/3/4
LVCMOS CMEMS Programmable Oscillator Series
Environmental Compliance and Package Information
Parameter
Test Condition
Mechanical Shock
MIL-STD-883, M2002 Cond B. (1,500g)
Mechanical Shock High g MIL-STD-883, M2002, Cond. E (10,000g)
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Temperature Cycle
JESD22, Method A104
Resistance to Solder Heat
MIL-STD-883, Method 2036
Contact Pads
Gold over Nickel/Palladium
®
Thermal Conditions
Parameter
Thermal
Impedance
Symbol
JA
Test Condition
3.2 x 5 mm, still air
2.5 x 3.2 mm, still air
2 x 2.5 mm, still air
Value
187
239
241
Unit
ºC/W
Clock Timing Characteristics
V
DD
= +1.71 V to +3.63 V, T
A
= -40 to 85 ºC unless stated otherwise.
Test Condition/Comment
Min
From V
DD
crossing 1.71 to first clock
—
From Stop mode
—
2, 3
Resume Time
T
RUN
From Sleep mode
—
From Doze mode
—
To Stop
—
Output Disable Time
2, 3
T
D
To Sleep/Doze
—
Frequency Update Time
2
T
NEW_FREQ
To New Frequency
—
1. Hold FS/OE high (strong or weak) during powerup for fastest time to clock.
2. Si501 and Si502 only. Si503 has frequency select (FS) only and does not support Stop, Doze or Sleep.
3. T
CLK
= clock period = 1/ F
CLK
.
Parameter
Startup Time
1
Symbol
T
SU
Typ
2.5
—
2.5
—
—
—
—
Max
4
1.5 x T
CLK
+ 35
5
2.55
1.5 x T
CLK
+ 35
225
5
Unit
ms
ns
ms
ns
s
ms
AC Waveforms
V
DD
1.71V
T
SU
Si501/2/3 Power On Time
R
UP
<1k
FS/OE
T
D
T
RUN
R
UP
<1k
R
UP
>20k
T
NEW_ FREQ
CLK
Hi-Z
Hi-Z
Si501/2 AC Waveform
R
UP
< 1k
FS
R
UP
> 20k
R
DOWN
> 20k
T
NEW_ FREQ
CLK
Hi-Z
T
NEW_ FREQ
Hi-Z
Si503 AC Waveform
Revision 0.72
www.silabs.com/cmems
3
Si501/2/3/4
LVCMOS CMEMS Programmable Oscillator Series
Applications Circuits
VDD
R
UP
FS/OE
®
VDD
VDD
VDD
~50K
FS/OE
R
DOWN
CLK
1
Si501/2
4
VDD
0.1uF
VDD
R
UP
1
Si503
4
VDD
0.1uF
Z
0
= 50
GND
2
3
CLK
R
S
Z
0
= 50
GND
2
3
CLK
CLK
R
S
Si501/2 Apps Circuit w/ Optional Series Resistor
Si503 Apps Circuit w/ Configurable Options
Notes:
1. Dotted line boxes show optional components depending on configuration options. See data sheet for additional information and for
applications using a microcontroller. Data sheet is available at
www.silabs.com/cmems.
2. Recommended series termination resistor (R
S
) = 24.9
for Z
0
= 50
.
Si502 FS/OE States and Resistor Values
FS/OE State
R
UP
Strong High
0
≤ R
UP
≤ 1 k
Weak High
20 k ≤ R
UP
≤ 200 k
Low
—
Clock Output
Frequency 1
Frequency 2
Hi-Z
Si503 FS States and Resistor Values
FS/OE State
R
UP
R
DOWN
Clock Output
No pop
Strong High
Frequency 1
0
≤ R
UP
≤ 1 k
No pop
Weak High 20 k ≤ R
UP
≤ 200 k
Frequency 2
Weak Low
No pop
20 k ≤ R
DOWN
≤ 200 k Frequency 3
Low
No pop
Frequency 4
0
≤ R
DOWN
≤ 1 k
Notes for both FS/OE tables above:
1. If the internal pull-up resistor order option is NOT selected, an MCU internal pull-up resistor or an external pull-up resistor should be used.
See data sheet for more information.
2. The parallel combination of all pull-up resistors on the FS/OE pin including the optional internal pull-up resistor must be > 20 k to select
Weak High.
3. If the Si50x internal pull-up resistor is enabled with no other external OE connections, the OE state will be detected as “Weak High”,
selecting Frequency 2 by default.
4
Revision 0.72
www.silabs.com/cmems
Si501/2/3/4
LVCMOS CMEMS Programmable Oscillator Series
Package Dimensions and Landing Patterns
3.2 mm x 5 mm 4-pin DFN Dimensions
4.00±0.15
#4
#3
®
3.2 mm x 5 mm 4-pin DFN Landing Pattern
2.54
3.20±0.15
1.20
2.20
0.94
#1
1.34
#2
1.60
1.20
1.50
0.90 Max
(top view)
Note: The 3.2 x 5 mm package is delivered as a 3.2 x 4 mm package and is drop-in compatible to industry-standard 3.2 x 5 landing patterns.
2.5 mm x 3.2 mm 4-pin DFN Dimensions
3.20±0.15
#4
#3
2.5 mm x 3.2 mm 4-pin DFN Landing Pattern
2.20
2.50±0.15
0.90
0.70
#1
#2
1.90
1.20
1.20
0.90 Max
(top view)
0.90
1.40
2 mm x 2.5 mm 4-pin DFN Dimensions
2.50±0.15
#4
#3
2 mm x 2.5 mm 4-pin DFN Landing Pattern
1.90
2.00±0.15
0.70
0.55
#1
#2
1.50
1.00
1.00
0.90 Max
(top view)
0.65
1.10
Revision 0.72
www.silabs.com/cmems
5
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