H8/3437 Series
H8/3437
HD6473437, HD6433437
H8/3436
HD6433436
H8/3434
HD6473434, HD6433434
H8/3434 F-ZTAT™
HD64F3434
H8/3437 F-ZTAT™
HD64F3437
Hardware Manual
ADE-602-077D
Rev. 5.0
5/20/98
Hitachi, Ltd.
MC-Setsu
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part
of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the
examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party
or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Contents
Preface ....... .....................................................................................................1
Section 1 Overview .........................................................................................3
1.1 Overview ......................................................................................................................... 3
1.2 Block Diagram................................................................................................................. 7
1.3 Pin Assignments and Functions........................................................................................ 8
1.3.1 Pin Arrangement................................................................................................. 8
1.3.2 Pin Functions ...................................................................................................... 9
Section 2 CPU................................................................................................21
2.1 Overview ......................................................................................................................... 21
2.1.1 Features .............................................................................................................. 21
2.1.2 Address Space..................................................................................................... 22
2.1.3 Register Configuration........................................................................................ 22
2.2 Register Descriptions ....................................................................................................... 23
2.2.1 General Registers................................................................................................ 23
2.2.2 Control Registers ................................................................................................ 23
2.2.3 Initial Register Values ........................................................................................ 24
2.3 Data Formats.................................................................................................................... 25
2.3.1 Data Formats in General Registers...................................................................... 25
2.3.2 Memory Data Formats ........................................................................................ 26
2.4 Addressing Modes............................................................................................................ 27
2.4.1 Addressing Mode................................................................................................ 27
2.4.2 Calculation of Effective Address......................................................................... 29
2.5 Instruction Set.................................................................................................................. 32
2.5.1 Data Transfer Instructions................................................................................... 34
2.5.2 Arithmetic Operations......................................................................................... 36
2.5.3 Logic Operations ................................................................................................ 37
2.5.4 Shift Operations.................................................................................................. 38
2.5.5 Bit Manipulations ............................................................................................... 39
2.5.6 Branching Instructions ........................................................................................ 43
2.5.7 System Control Instructions ................................................................................ 45
2.5.8 Block Data Transfer Instruction .......................................................................... 46
2.6 CPU States....................................................................................................................... 47
2.6.1 Overview ............................................................................................................ 47
2.6.2 Program Execution State..................................................................................... 48
2.6.3 Exception-Handling State ................................................................................... 48
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2.6.4 Power-Down State .............................................................................................. 48
2.7 Access Timing and Bus Cycle.......................................................................................... 49
2.7.1 Access to On-Chip Memory (RAM and ROM) ................................................... 49
2.7.2 Access to On-Chip Register Field and External Devices ..................................... 50
Section 3 MCU Operating Modes and Address Space .................................... 53
3.1 Overview ......................................................................................................................... 53
3.1.1 Mode Selection................................................................................................... 53
3.1.2 Mode and System Control Registers ................................................................... 53
3.2 System Control Register (SYSCR)................................................................................... 54
3.3 Mode Control Register (MDCR) ...................................................................................... 56
3.4 Address Space Map in Each Operating Mode................................................................... 57
Section 4 Exception Handling ........................................................................ 61
4.1 Overview ......................................................................................................................... 61
4.2 Reset................................................................................................................................ 61
4.2.1 Overview ............................................................................................................ 61
4.2.2 Reset Sequence................................................................................................... 61
4.2.3 Disabling of Interrupts after Reset ...................................................................... 63
4.3 Interrupts ......................................................................................................................... 64
4.3.1 Overview ............................................................................................................ 64
4.3.2 Interrupt-Related Registers ................................................................................. 66
4.3.3 External Interrupts .............................................................................................. 70
4.3.4 Internal Interrupts ............................................................................................... 70
4.3.5 Interrupt Handling .............................................................................................. 71
4.3.6 Interrupt Response Time..................................................................................... 76
4.3.7 Precaution........................................................................................................... 77
4.4 Note on Stack Handling ................................................................................................... 78
Section 5 Wait-State Controller...................................................................... 79
5.1 Overview ......................................................................................................................... 79
5.1.1 Features .............................................................................................................. 79
5.1.2 Block Diagram ................................................................................................... 79
5.1.3 Input/Output Pins................................................................................................ 80
5.1.4 Register Configuration........................................................................................ 80
5.2 Register Description......................................................................................................... 80
5.2.1 Wait-State Control Register (WSCR).................................................................. 80
5.3 Wait Modes ..................................................................................................................... 82
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Section 6 Clock Pulse Generator ....................................................................85
6.1 Overview ......................................................................................................................... 85
6.1.1 Block Diagram.................................................................................................... 85
6.1.2 Wait-State Control Register (WSCR).................................................................. 85
6.2 Oscillator Circuit ............................................................................................................. 86
6.3 Duty Adjustment Circuit .................................................................................................. 90
6.4 Prescaler .......................................................................................................................... 90
Section 7 I/O Ports .........................................................................................91
7.1 Overview ......................................................................................................................... 91
7.2 Port 1 ............................................................................................................................... 94
7.2.1 Overview ............................................................................................................ 94
7.2.2 Register Configuration and Descriptions............................................................. 95
7.2.3 Pin Functions in Each Mode ............................................................................... 97
7.2.4 Input Pull-Up Transistors .................................................................................... 98
7.3 Port 2 ............................................................................................................................... 99
7.3.1 Overview ............................................................................................................ 99
7.3.2 Register Configuration and Descriptions............................................................. 100
7.3.3 Pin Functions in Each Mode ............................................................................... 102
7.3.4 Input Pull-Up Transistors .................................................................................... 103
7.4 Port 3 ............................................................................................................................... 104
7.4.1 Overview ............................................................................................................ 104
7.4.2 Register Configuration and Descriptions............................................................. 105
7.4.3 Pin Functions in Each Mode ............................................................................... 107
7.4.4 Input Pull-Up Transistors .................................................................................... 108
7.5 Port 4 ............................................................................................................................... 108
7.5.1 Overview ............................................................................................................ 108
7.5.2 Register Configuration and Descriptions............................................................. 109
7.5.3 Pin Functions ...................................................................................................... 111
7.6 Port 5 ............................................................................................................................... 113
7.6.1 Overview ............................................................................................................ 113
7.6.2 Register Configuration and Descriptions............................................................. 113
7.6.3 Pin Functions ...................................................................................................... 115
7.7 Port 6 ............................................................................................................................... 116
7.7.1 Overview ............................................................................................................ 116
7.7.2 Register Configuration and Descriptions............................................................. 116
7.7.3 Pin Functions ...................................................................................................... 119
7.7.4 Input Pull-Up Transistors .................................................................................... 121
7.8 Port 7 ............................................................................................................................... 122
7.8.1 Overview ............................................................................................................ 122
7.8.2 Register Configuration and Descriptions............................................................. 122
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