The CY2PP3210 is a low-skew, low propagation delay dual
1-to-5 differential fanout buffer targeted to meet the require-
ments of high-performance clock and data distribution applica-
tions. The device is implemented on SiGe technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to 1.5
GHz.
The device features two differential input paths that are differ-
ential internally. The CY2PP3210 may function not only as a
differential clock buffer but also as a signal-level translator and
fanout distributing a single-ended signal. An external bias pin,
VBB, is provided for this purpose. In such an application, the
VBB pin should be connected to either one of the CLKA# or
CLKB# inputs and bypassed to ground via a 0.01-µF capacitor.
Traditionally, in ECL, it is used to provide the reference level
to a receiving single-ended input that might have a differential
bias point.
Since the CY2PP3210 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3210 delivers consistent performance
over various platforms.
Block Diagram
QA0
QA0#
QA1
QA1#
QA2
QA2#
V
EE
Pin Configuration
CLKA
CLKA#
V
CC
QA3
QA3#
QA4
QA4#
QB0
QB0#
QB1
QB1#
QB2
QB2#
VCC
NC
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
VCC
QA0
QA0#
QA1
QA1#
QA2
QA2#
VCC
CY2PP3210
24
23
22
21
20
19
18
17
QA3
QA3#
QA4
QA4#
QB0
QB0#
QB1
QB1#
CLKB
CLKB#
V
EE
QB3
QB3#
QB4
QB4#
VBB
Cypress Semiconductor Corporation
Document #: 38-07508 Rev.*C
•
3901 North First Street
•
San Jose
,
CA 95134
VCC
QB4#
QB4
QB3#
QB3
QB2#
QB2
VCC
9
10
11
12
13
14
15
16
V
CC
•
408-943-2600
Revised July 28, 2004
FastEdge™ Series
CY2PP3210
Pin Definitions
[1, 2, 3]
Pin
2
3
4
5
6
7
8
1,9,16,25,32
31,29,27,24,22
30,28,26,23,21
20,18,15,13,11
19,17,14,12,10
Name
NC
CLKA,
CLKA#
VBB
[3]
CLKB,
CLKB#
VEE
[2]
VCC
QA(0:4)
QA#(0:4)
QB(0:4)
QB#(0:4)
I,PD
O
I,PD
–PWR
+PWR
O
O
O
O
ECL/PECL
Bias
ECL/PECL
Power
Power
I,PD/PU ECL/PECL
I/O
[1]
Type
No connect.
ECL/PECL Differential Input Clocks.
ECL/PECL Differential Input Clocks.
Reference Voltage Output.
ECL/PECL Differential Input Clocks.
ECL/PECL Differential Input Clocks.
Negative Supply.
Positive Supply.
Description
I,PD/PU ECL/PECL
ECL/PECL
True output
ECL/PECL
Complement output
ECL/PECL
True output
ECL/PECL
Complement output
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP3210. The agency name and relevant specification is
listed below in
Table 2.
Table 1.
Agency Name
JEDEC
Specification
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
883E Method 1012.1 (Thermal Theta JC)
Mil-Spec
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), V
EE
is either –3.3V or –2.5V and V
CC
is connected to GND (0V). In PECL mode (positive power supply mode),
V
EE
is connected to GND (0V) and V
CC
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
CC
)
and are between V
CC
and V
EE
.
3. V
BB
is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
Document #: 38-07508 Rev.*C
Page 2 of 9
FastEdge™ Series
CY2PP3210
Absolute Maximum Ratings
Parameter
V
CC
V
EE
T
S
T
J
ESD
h
M
SL
Description
Positive Supply Voltage
Negative Supply Voltage
Temperature, Storage
Temperature, Junction
ESD Protection
Moisture Sensitivity Level
Assembled Die
Condition
Non-Functional
Non-Functional
Non-Functional
Non-Functional
Human Body Model
2000
3
50
Min.
–0.3
-4.6
–65
Max.
4.6
0.3
+150
150
Unit
V
V
°C
°C
V
N.A.
gates
Gate Count Total Number of Used Gates
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter
I
BB
LU
I
T
A
Ø
Jc
Ø
Ja
I
EE
C
IN
L
IN
V
IN
V
TT
V
OUT
I
IN
Description
Output Reference Current
Latch Up Immunity
Temperature, Operating Ambient
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Maximum Quiescent Supply Current
Input pin capacitance
Pin Inductance
Input Voltage
Output Termination Voltage
Output Voltage
Input Current
[7]
Relative to V
CC[6]
Relative to V
CC[6]
Relative to V
CC[6]
V
IN
= V
IL
, or V
IN
= V
IH
–0.3
–0.3
V
CC
– 2
V
CC
+ 0.3
l150l
Condition
Relative to V
BB
Functional, typical
Functional
Functional
Functional
V
EE
pin
[5]
–
–
–40
29
[4]
76
[4]
130
3
1
V
CC
+ 0.3
Min.
–
100
+85
Max.
|200|
Unit
uA
mA
°C
°C/W
°C/W
mA
pF
nH
V
V
V
uA
PECL DC Electrical Specifications
Parameter
V
CC
V
CMR
V
OH
V
OL
V
IH
V
IL
Description
Operating Voltage
Differential Cross Point Voltage
[8]
Output High Voltage
Output Low Voltage
V
CC
= 3.3V ± 5%
V
CC
= 2.5V ± 5%
Input Voltage, High
Condition
2.5V ± 5%, V
EE
= 0.0V
3.3V ± 5%, V
EE
= 0.0V
Differential operation
I
OH
= –30 mA
[9]
I
OL
= –5 mA
[9]
Single-ended operation
Min.
2.375
3.135
1.2
V
CC
– 1.25
V
CC
– 1.995
V
CC
–1.995
V
CC
– 1.165
[10]
Max.
2.625
3.465
V
CC
V
CC
– 0.7
V
CC
– 1.5
V
CC
– 1.3
V
CC
– 0.880
[10]
Unit
V
V
V
V
V
V
V
V
V
Input Voltage, Low
Single-ended operation
V
CC
– 1.945
V
CC
– 1.625
[3]
[6]
V
BB
Output Reference Voltage
Relative to V
CC
V
CC
– 1.620
V
CC
– 1.220
Notes:
4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5. Power Calculation: V
CC
* I
EE
+0.5 (I
OH
+ I
OL
) (V
OH
– V
OL
) (number of differential outputs used); I
EE
does not include current going off chip.
6. where V
CC
is 3.3V±5% or 2.5V±5%
7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8. Refer to Figure 1
9. Equivalent to a termination of 50Ω to VTT. I
OHMIN
=(V
OHMIN
-V
TT
)/50; I
OHMAX
=(V
OHMAX
-V
TT
)/50; I
OLMIN
=(V
OLMIN
-V
TT
)/50; I
OLMAX
=(V
OLMAX
-V
TT
)/50;
10. V
IL
will operate down to V
EE
; V
IH
will operate up to V
CC
Document #: 38-07508 Rev.*C
Page 3 of 9
FastEdge™ Series
CY2PP3210
ECL DC Electrical Specifications
Parameter
V
EE
V
CMR
V
OH
V
OL
V
IH
V
IL
V
BB[3]
Description
Negative Power Supply
Differential cross point voltage
[8]
Output High Voltage
Output Low Voltage
V
EE
= –3.3V ± 5%
V
EE
= –2.5V ± 5%
Input Voltage, High
Input Voltage, Low
Output Reference Voltage
Condition
–2.5V ± 5%, V
CC
= 0.0V
–3.3V ± 5%, V
CC
= 0.0V
Differential operation
I
OH
= –30 mA
[9]
I
OL
= –5 mA
[9]
Single-ended operation
Single-ended operation
Min.
–2.625
–3.465
V
EE
+ 1.2
–1.25
–1.995
–1.995
–1.165
–1.945
[10]
Max.
–2.375
–3.135
0V
–0.7
–1.5
–1.3
–0.880
[10]
–1.625
– 1.220
Unit
V
V
V
V
V
V
V
– 1.620
AC Electrical Specifications
Parameter
V
PP
F
CLK
T
PD
Vo
V
CMRO
tsk
(0)
tsk
(PP)
T
PER
tsk
(P)
T
R
,T
F
Description
Differential Input
Input Frequency
Propagation Delay CLKA or CLKB to
Output pair
Output Voltage (peak-to-peak; see
Figure 2)
Output Common Voltage Range (typ.)
Output-to-output Skew
Part-to-Part Output Skew
Output Period Jitter
Output Pulse
(rms)
[12]
Skew
[13]
660 MHz
[11]
, See Figure 3
660 MHz
660 MHz
660 MHz
[11]
[11]
[11]
,
Condition
Differential operation
50% duty cycle Standard load
660 MHz
[11]
Min.
0.1
280
Max.
1.3
1.5
750
–
Unit
V
GHz
ps
Voltage
[8]
< 1 GHz
0.375
V
CC
– 1.425
–
–
–
See Figure 3
–
0.08
V
V
ps
ps
ps
ps
ns
50
150
0.8
50
0.3
Output Rise/Fall Time (see Figure 2)
660 MHz 50% duty cycle
Differential 20% to 80%
Timing Definitions
VCC
VCM R Max = VCC
VIH
VPP
VPP range
0.1V - 1.3V
VCM R
VIL
VCMR M in = VEE + 1.2
VEE
Figure 1. PECL/ECL Input Waveform Definitions
Notes:
11. 50% duty cycle; standard load; differential operation
12. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
13. Output pulse skew is the absolute difference of the propagation delay times: | t
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