54ACT399 Quad 2-Port Register
August 1998
54ACT399
Quad 2-Port Register
General Description
The ’AC/ACT399 is the logical equivalent of a quad 2-input
multiplexer feeding into four edge-triggered flip-flops. A com-
mon Select input determines which of the two 4-bit words is
accepted. The selected data enters the flip-flop on the rising
edge of the clock.
Features
n
n
n
n
n
I
CC
reduced by 50%
Select inputs from two data sources
Fully positive edge-triggered operation
Outputs source/sink 24 mA
ACT399 has TTL-compatible inputs
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100356-1
IEEE/IEC
DS100356-3
Pin Assignment
for LCC
DS100356-5
DS100356-2
Pin Names
S
CP
I
0a
–I
0d
I
1a
–I
1d
Q
a
–Q
d
Description
Common Select Input
Clock Pulse Input
Data Inputs from Source 0
Data Inputs from Source 1
Register True Outputs
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100356
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Functional Description
The ’AC/ACT399 is a high-speed quad 2-port register. It se-
lects four bits of data from either of two sources (Ports) un-
der control of a common Select input (S). The selected data
is transferred to a 4-bit output register synchronous with the
LOW-to-HIGH transition of the Clock input (CP). The 4-bit
D-type output register is fully edge-triggered. The Data in-
puts (I
0x
, I
1x
) and Select input (S) must be stable only a setup
time prior to and hold time after the LOW-to-HIGH transition
of the Clock input for predictable operation.
Function Table
Inputs
S
L
L
H
H
I
0
L
H
X
X
I
1
X
X
L
H
CP
N
N
N
N
Outputs
Q
L
H
L
H
Q
H
L
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Clock Transition
Logic Diagram
DS100356-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source or
Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
Junction Temperature (T
J
)
CDIP
+175˚C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54ACT
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
±
50 mA
±
50 mA
−65˚C to +150˚C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
®
circuits outside databook specifications.
DC Electrical Characteristics for ’ACT Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
4.5
5.5
4.5
5.5
4.5
5.5
54ACT
T
A
= −55˚C to
+125˚C
Guaranteed
Limits
2.0
2.0
0.8
0.8
4.4
5.4
(Note 2)
V
IN
= V
IL
or V
IH
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
3.70
4.70
0.1
0.1
(Note 2)
V
IN
= V
IL
or V
IH
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
(Note 3)
Output Current
Maximum Quiescent
Supply Current
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Units
Conditions
V
V
V
V
OUT
= 0.1V
or V
CC
−0.1V
V
OUT
= 0.1V
or V
CC
− 0.1V
I
OUT
= −50 µA
V
V
I
OH
= −24 mA
I
OH
= −24 mA
I
OUT
= 50 µA
0.50
0.50
V
µA
mA
mA
mA
µA
I
OL
= 24 mA
I
OL
= 24 mA
V
I
= V
CC
, GND
V
I
= V
CC
−2.1V
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or Ground
5.5
5.5
5.5
5.5
5.5
±
1.0
1.6
50
−50
80.0
3
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AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 4)
Min
f
max
t
PLH
t
PHL
Input Clock Frequency
Propagation Delay
CP to Q
Propagation Delay
CP to Q
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V
54ACT
T
A
, V
CC
= Mil
C
L
= 50 pF
Max
MHz
10.0
10.0
ns
ns
Units
Fig.
No.
5.0
5.0
5.0
90
1.5
1.5
AC Operating Requirements
V
CC
Symbol
Parameter
(V)
(Note 5)
54ACT
T
A
= −55˚C
to +125˚C
C
L
= 50 pF
Guaranteed
Minimum
t
s
t
h
t
s
t
h
t
w
Setup Time, HIGH or LOW
I
n
to CP
Hold Time, HIGH or LOW
I
n
to CP
Setup Time, HIGH or LOW
S to CP
Hold Time, HIGH or LOW
S to CP
CP Pulse Width,
HIGH or LOW
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
Units
Fig.
No.
5.0
5.0
5.0
5.0
5.0
3.5
3.0
6.0
2.5
5.0
ns
ns
ns
ns
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
30
Units
pF
pF
Conditions
V
CC
= OPEN
V
CC
= 5.0V
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4
Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
5
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