CAT93HC46
1-kb High Speed Microwire Serial EEPROM
FEATURES
s
High speed operation: 4 MHz @ 5.0 V
s
1.8 to 5.5 volt operation
s
Selectable x8 or x16 word organization
s
Sequential Read
s
Software write protection
s
Power-up inadvertent write protection
s
Low power CMOS technology
s
1,000,000 program/erase cycles
s
100 year data retention
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Industrial and extended temperature ranges
s
8-Lead PDIP, SOIC, MSOP and TSSOP
packages
DESCRIPTION
The CAT93HC46 is a 1-kb Serial EEPROM memory
device which is configured as registers of either 16 bits
(ORG pin at V
CC
) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
PIN CONFIGURATION
DIP Package (P, L)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
SOIC Package (J, W)
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
SOIC Package (S, V) MSOP Package (R, Z)
CS
SK
DI
DO
1
2
3
4
CS
SK
DI
DO
i
D
8
7
6
5
VCC
NC
ORG
GND
TSSOP Package (U, Y)
1
2
3
4
8
7
6
5
c
s
CS
SK
DI
DO
1
2
3
4
8
7
6
5
i
t
n
o
VCC
NC
ORG
GND
u
n
CS
SK
DI
DO
V
CC
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, SOIC,
MSOP or TSSOP packages.
FUNCTIONAL SYMBOL
VCC
d
e
a
P
t
r
ORG
DI
CAT93HC46
SK
CS
DO
VSS
PIN FUNCTIONS
Pin Name
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
1.8 to 5.5 V Power Supply
Ground
Memory Organization
No Connection
VCC
NC
ORG
GND
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
GND
ORG
NC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1008,Rev. H
CAT93HC46
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Pin with Respect to Ground
(1)
.... -2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ................ -2.0 V to 7.0 V
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Typ
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
D.C. OPERATING CHARACTERISTICS
Industrial Temperature Range (-40°C to 85°C)
Symbol
I
CC1
I
CC2
I
SB1
I
SB2(5)
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current (Write)
Power Supply Current (Read)
Standby Supply Current (x8)
Standby Supply Current (x16)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Note:
(1) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1 V to V
CC
+ 1 V.
(5) Standby Current (ISB
2
) = 0
µA
(<900 nA).
i
D
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
2.4
Output High Voltage
Output Low Voltage
c
s
i
t
n
o
Min
-0.1
2
0
V
CC
x 0.7
V
CC
- 0.2
Limits
Typ
0
u
n
Max
2
200
10
10
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
0.2
d
e
100
Units
mA
µA
µA
µA
µA
µA
V
2000
a
P
Max
Test Conditions
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.8 V
≤
V
CC
< 4.5 V
1.8V
≤
V
CC
< 4.5 V
Units
Cycles/Byte
Years
Volts
mA
t
r
f
SK
= 4 MHz, V
CC
= 5.0 V
f
SK
= 4 MHz, V
CC
= 5.0 V
CS = GND, ORG=GND
CS = GND, ORG = Float or V
CC
V
IN
= 0 V to V
CC
, CS = GND
V
OUT
= 0 V to V
CC
, CS = GND
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 2.1 mA
4.5 V
≤
V
CC
< 5.5 V, I
OH
= -400
µA
1.8 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
Output High Voltage
1.8 V
≤
V
CC
< 4.5 V, I
OH
= -100
µA
Doc. No. 1008, Rev. H
2
CAT93HC46
POWER-UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
A.C. CHARACTERISTICS
Industrial Temperature Range (-40°C to 85°C)
1.8 V - 5.5 V
Symbol
SK
MAX
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
CSMIN
t
SKHI
t
SKLOW
t
SV
t
EW
Parameter
Maximum Clock Frequency
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Min
DC
240
0
240
240
480
480
Max
1
2.5 V - 5.5 V
Min
DC
120
0
120
120
Max
2
4.5 V - 5.5 V
Min
DC
60
Max
4
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Program/Erase Pulse Width
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
A.C. TEST CONDITIONS
Input Pulse Voltages
Input Rise and Fall Times
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
i
D
c
s
i
t
n
o
240
480
240
≤
10 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
V
CC
x 0.5
240
480
5
u
n
120
240
120
240
240
120
d
e
60
60
60
120
60
0
120
120
60
a
P
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Conditions
t
r
Test
(3)
CL = 100 pF
240
5
120
5
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
1.8 V
≤
V
CC
≤
4.5 V
1.8 V
≤
V
CC
≤
4.5 V
V
CC
x 0.2 to V
CC
x 0.8
3
Doc. No. 1008, Rev. H
CAT93HC46
DEVICE OPERATION
The CAT93HC46 is a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93HC46 can be organized as registers of either
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the operation of the device.
The CAT93HC46 operates on a single power supply and
will generate on chip the high voltage required during
write operation.
Instructions, addresses, and data are clocked into the DI
pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state, except when reading
data from the device, or when checking the ready/busy
status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state by shifting a dummy “1” into the DI pin. The DO pin
will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin
and the DO pin are to be tied together to form a common
DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/
word address (an additional bit when organized X8) and
for write operations a 16-bit data field (8-bit for X8
organization).
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit Opcode
1
1
1
1
1
1
1
10
11
01
00
00
00
Address
x8
x16
A6-A0
A5-A0
x8
A6-A0
A6-A0
11XXXXX
00XXXXX
10XXXXX
01XXXXX
Figure 1. Sychronous Data Timing
tSKHI
tSKLOW
tCSH
SK
DI
i
D
c
s
00
VALID
i
t
n
o
A5-A0
A5-A0
11XXXX
00XXXX
10XXXX
01XXXX
tDIS
D7-D0
u
n
Data
x16
Comments
Read Address AN–A0
Clear Address AN–A0
d
e
a
P
t
r
D15-D0 Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
D15-D0 Write All Addresses
D7-D0
tDIS
VALID
tDIH
tCSS
CS
tPD0,tPD1
DATA VALID
tCSMIN
DO
Doc. No. 1008, Rev. H
4
CAT93HC46
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state; after an initial
dummy zero bit, data will be shifted out, MSB first. The
output will toggle on the rising edge of the SK clock and
will be stable after the specified time delay (t
PD0
or t
PD1
)
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and data,
the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
. The falling edge of CS will start the
self-timed clear and data store cycle into the specified
memory location. The clocking of the SK pin is not
necessary after the device has entered the self-timed
mode. (Note 1.) The ready/busy status of the CAT93HC46
can be determined by selecting the device and polling
the DO pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
Erase
Figure 2a. Read Instruction Timing
SK
CS
DI
1
DO
Figure 2b. Sequential Read Instruction Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
i
D
CS
DI
DO
c
s
1
0
1
1
AN
HIGH-Z
i
t
n
o
AN—1
tPD0
AN
0
AN–1
HIGH-Z
Dummy 0
u
n
0
DN
DN—
1
A0
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
CSMIN
. The falling edge of CS will start the self-timed
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self-timed mode. (Note 1.) The ready/busy
status of the CAT93HC46 can be determined by selecting
the device and polling the DO pin. Once cleared, the
content of a cleared location returns to a logical “1” state.
d
e
D1
a
P
STANDBY
t
r
tCS MIN
A0
tHZ
HIGH-Z
D0
Don't Care
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
5
Doc. No. 1008, Rev. H
FPGA/CPLD
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