LXT973
10/100 Mbps 2-Port Fast Ethernet PHY Transceiver
Preliminary Datasheet
The LXT973 is an IEEE-compliant, 2-port, Fast Ethernet PHY transceiver that directly supports
both 100BASE-TX and 10BASE-T applications. Each port provides a Media Independent
Interface (MII) for easy attachment to 10 Mbps and 100 Mbps Media Access Controllers
(MACs). The LXT973 device also provides a pseudo-ECL (PECL) interface per port for use
with 100BASE-FX fiber networks. The LXT973 incorporates the auto-MDIX feature, allowing
it to automatically detect and switch the polarity of the lines.
The LXT973 is an ideal building block for systems that require two Ethernet ports, such as
Internet Protocol (IP) Telephones, Twisted-Pair (TX)-to-Fiber (FX) converter modules, and for
telecom applications, such as Telecom Central Office (TCO) and Customer Premise Equipment
(CPE) devices.
The LXT973 supports full-duplex operation at both 10 Mbps and 100 Mbps. Its operating modes
can be set using auto-negotiation, parallel detect, or manual control.
Product Features
s
s
s
s
s
s
s
s
2-port Fast Ethernet PHY
2.5V operation
3.3V operation I/O compatibility
Low power consumption; 250 mW per
port typical
Full 2-port MII interface with extended
registers
Automatic MDI/MDIX switch over
capability
Signal Quality Error (SQE) enable/disable
100BASE-FX fiber-optic capability on
both ports
s
s
s
s
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Supports both auto-negotiation systems
and legacy systems without auto-
negotiation capability
Support for Next Page
20 MHz Register Access*
Configurable via MDIO port or external
control pins
Integrated termination resistors
100-pin Plastic Quad Flat Package (PQFP)
— LXT973QC - Commercial (0
°
to 70
°
C
ambient).
— LXT973QE - Extended (-40
°
to 85
°
C
ambient).
Note:
20 MHz Register Access will be verified before final production release of
product.
For technical assistance on this product, please call 1-800-628-8686,
or send an e-mail to support@mailbox.intel.com.
Order Number: 249426-001
May 2001
Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT973 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
2
Preliminary Datasheet
Document #: 249426
Revision #: 001
Rev. Date: 05/18/01
LXT973 - 10/100 Mbps 2- Port Fast Ethernet PHY Transceiver
Contents
1.0 Pin Assignments and Signal Descriptions
................................................................. 10
2.0 Signal Descriptions
.............................................................................................................. 14
3.0 Functional Description
........................................................................................................ 19
3.1
3.2
Introduction ......................................................................................................................... 19
3.1.1 Comprehensive Functionality ................................................................................ 19
Interface Descriptions ......................................................................................................... 19
3.2.1 10/100 Mbps Network Interface ............................................................................. 19
3.2.1.1 Twisted-Pair Interface ............................................................................ 20
3.2.1.2 MDI Crossover (MDIX)........................................................................... 21
3.2.1.3 Fiber Interface........................................................................................ 21
MII Operation ...................................................................................................................... 21
3.3.1 MII Clocks .............................................................................................................. 21
3.3.2 Transmit Enable..................................................................................................... 21
3.3.3 Receive Data Valid ................................................................................................ 21
3.3.4 Carrier Sense......................................................................................................... 22
3.3.5 Error Signals .......................................................................................................... 22
3.3.6 Collision ................................................................................................................. 22
3.3.7 Loopback ............................................................................................................... 22
3.3.7.1 Operational Loopback............................................................................ 22
3.3.7.2 Test Loopback ....................................................................................... 22
3.3.8 Configuration Management Interface .................................................................... 23
3.3.8.1 MII Management Interface ..................................................................... 23
3.3.8.2 MII Addressing ....................................................................................... 24
3.3.8.3 Hardware Control Interface.................................................................... 25
Operating Requirements..................................................................................................... 25
3.4.1 Power Requirements ............................................................................................. 25
3.4.2 Clock Requirements .............................................................................................. 25
3.4.2.1 Reference Clock / External Oscillator .................................................... 25
3.4.2.2 MDIO Clock............................................................................................ 26
Initialization ......................................................................................................................... 26
3.5.1 MDIO Control Mode ............................................................................................... 26
3.5.2 Hardware Control Mode......................................................................................... 26
3.5.3 Power-Down Mode ................................................................................................ 27
3.5.3.1 Hardware Power-Down.......................................................................... 27
3.5.3.2 Software Power-Down ........................................................................... 27
3.5.4 Reset .....................................................................................................................27
3.5.5 Hardware Configuration Settings ........................................................................... 28
Link Establishment.............................................................................................................. 28
3.6.1 Auto-Negotiation .................................................................................................... 28
3.6.1.1 Base Page Exchange ............................................................................ 29
3.6.1.2 Next Page Exchange ............................................................................. 29
3.6.1.3 Controlling Auto-Negotiation .................................................................. 29
3.6.1.4 Link Criteria............................................................................................ 29
3.6.1.5 Parallel Detection ................................................................................... 29
Network Media/Protocol Support ........................................................................................ 30
3.7.1 10/100 Mbps Network Interface ............................................................................. 30
3.3
3.4
3.5
3.6
3.7
Preliminary Datasheet
Document #: 249426
Revision #: 001
Rev. Date: 05/18/01
3
LXT973 - 10/100 Mbps 2- Port Fast Ethernet PHY Transceiver
3.8
3.9
3.10
3.7.2 Twisted-Pair Interface............................................................................................ 30
3.7.3 Fiber Interface........................................................................................................ 31
3.7.4 Fault Detection and Reporting ............................................................................... 31
3.7.5 Remote Fault ......................................................................................................... 31
3.7.6 Far-End Fault......................................................................................................... 31
100 Mbps Operation ........................................................................................................... 32
3.8.1 100BASE-X Network Operations........................................................................... 32
3.8.2 100BASE-X Protocol Sublayer Operations............................................................ 33
3.8.3 PCS Sublayer ........................................................................................................ 33
3.8.3.1 Preamble Handling ................................................................................ 33
3.8.3.2 Dribble Bits............................................................................................. 33
3.8.4 PMA Sublayer........................................................................................................ 34
3.8.4.1 Link Failure Override.............................................................................. 35
3.8.4.2 Carrier Sense......................................................................................... 35
3.8.4.3 Twisted-Pair PMD Sublayer................................................................... 35
3.8.4.4 Scrambler/Descrambler ......................................................................... 35
3.8.4.5 Baseline Wander Correction .................................................................. 35
3.8.5 Fiber PMD Sublayer .............................................................................................. 36
3.8.5.1 Far End Fault Indications ....................................................................... 36
10 Mbps Operation ............................................................................................................. 36
3.9.1 Polarity Correction ................................................................................................. 36
3.9.2 Dribble Bits ............................................................................................................ 37
3.9.3 Link Test ................................................................................................................ 37
3.9.4 Link Failure ............................................................................................................ 37
3.9.5 Jabber.................................................................................................................... 37
Monitoring Operations ........................................................................................................ 37
3.10.1 Monitoring Auto-Negotiation .................................................................................. 37
3.10.2 Per-Port LED Driver Functions .............................................................................. 37
4.0 Application Information
...................................................................................................... 39
4.1
Design Recommendations.................................................................................................. 39
4.1.1 General Design Guidelines.................................................................................... 39
4.1.2 Power Supply Filtering........................................................................................... 39
4.1.3 Power and Ground Plane Layout Considerations.................................................. 40
4.1.3.1 Chassis Ground ..................................................................................... 40
4.1.4 MII Terminations .................................................................................................... 40
4.1.5 The Fiber Interface ................................................................................................ 40
4.1.6 Twisted-Pair Interface............................................................................................ 41
4.1.6.1 Magnetics Information............................................................................ 41
Typical Application Circuits................................................................................................. 42
Initialization ......................................................................................................................... 44
MDIO Control Mode............................................................................................................ 45
Manual Control Mode ......................................................................................................... 45
4.2
4.3
4.4
4.5
5.0
Configuration
......................................................................................................................... 46
6.0 Auto Negotiation
.................................................................................................................... 47
7.0 Auto MDI/MDIX
........................................................................................................................ 48
8.0 100 Mbps Operation
............................................................................................................. 48
8.1
Displaying Symbol Errors ................................................................................................... 49
4
Preliminary
Datasheet
Document #: 249426
Revision #: 001
Rev. Date: 05/18/01
LXT973 - 10/100 Mbps 2- Port Fast Ethernet PHY Transceiver
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
4B/5B Encoder Bypass .......................................................................................... 50
Scrambler Seeding ................................................................................................ 51
Scrambler Bypass.................................................................................................. 51
100BASE-T Link Failure Criteria and Override ...................................................... 51
Baseline Wander Correction.................................................................................. 51
Programmable Tx Slew Rate ................................................................................. 51
9.0 Fiber Interface
......................................................................................................................... 52
10.0 10 Mbps Operation
................................................................................................................ 53
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
Link Test ............................................................................................................................. 53
10Base-T Link Failure Criteria and Override ...................................................................... 53
SQE (Heartbeat) ................................................................................................................. 54
Jabber................................................................................................................................. 54
Polarity Correction .............................................................................................................. 54
Dribble Bits ......................................................................................................................... 54
Transmit Polarity Control .................................................................................................... 54
Phy Address ....................................................................................................................... 54
11.0 Clock Generation
................................................................................................................... 55
11.1
External Oscillator............................................................................................................... 55
12.0 Register Definitions
.............................................................................................................. 57
13.0 Magnetics Information
......................................................................................................... 67
14.0 Preliminary Test Specifications
....................................................................................... 68
15.0 Timing Diagrams
.................................................................................................................... 72
16.0 Mechanical Specifications
................................................................................................. 83
Figures
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
LXT973 Block Diagram................................................................................................................. 9
LXT973 Pin Assignments ........................................................................................................... 10
LXT973 Interfaces ..................................................................................................................... 20
Loopback Paths ......................................................................................................................... 23
Management Interface Read Frame Structure .......................................................................... 24
Management Interface Write Frame Structure .......................................................................... 24
Port Address Scheme................................................................................................................. 25
Auto-Negotiation Operation ....................................................................................................... 30
100BASE-X Frame Format ........................................................................................................ 32
Protocol Sublayers ..................................................................................................................... 33
LED Pulse Stretching ................................................................................................................. 38
Typical LED Implementation ...................................................................................................... 38
Power and Ground Supply Connections .................................................................................... 42
Typical Twisted-Pair Interface ................................................................................................... 43
Typical Fiber Interface ............................................................................................................... 44
Typical MII Interface .................................................................................................................. 44
LXT973 Initialization Sequence .................................................................................................. 45
100BASE-TX Frame Format....................................................................................................... 49
100BASE-TX Data Path ............................................................................................................. 49
Preliminary Datasheet
Document #: 249426
Revision #: 001
Rev. Date: 05/18/01
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