HN58C256A Series
HN58C257A Series
256k EEPROM (32-kword
×
8-bit)
Ready/Busy and
RES
function (HN58C257A)
REJ03C0148-0500Z
(Previous ADE-203-410D (Z) Rev. 4.0)
Rev. 5.00
Nov. 17. 2003
Description
Renesas Technology
's
HN58C256A and HN58C257A are electrically erasable and programmable ROMs
organized as 32768-word
×
8-bit. They have realized high speed low power consumption and high reliability
by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.
Features
•
Single 5 V supply: 5 V
±10%
•
Access time: 85 ns/100 ns (max)
•
Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110
µW
(max)
•
On-chip latches: address, data,
CE, OE, WE
•
Automatic byte write: 10 ms max
•
Automatic page write (64 bytes): 10 ms max
•
Ready/Busy (only the HN58C257A series)
•
Data
polling and Toggle bit
•
Data protection circuit on power on/off
•
Conforms to JEDEC byte-wide standard
•
Reliable CMOS with MNOS cell technology
•
10 erase/write cycles (in page mode)
5
•
10 years data retention
•
Software data protection
•
Write protection by
RES
pin (only the HN58C257A series)
•
Industrial versions (Temperatur range:
−20
to 85°C and – 40 to 85°C) are also available.
•
There are also lead free products.
Rev.5.00, Nov. 17.2003, page 1 of 23
HN58C256A Series, HN58C257A Series
Ordering Information
Type No.
HN58C256AP-85
HN58C256AP-10
HN58C256AFP-85
HN58C256AFP-10
HN58C256AT-85
HN58C256AT-10
HN58C257AT-85
HN58C257AT-10
HN58C256AFP-85E
HN58C256AFP-10E
HN58C256AT-85E
HN58C256AT-10E
HN58C257AT-85E
HN58C257AT-10E
Access time
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
Package
600 mil 28-pin plastic DIP (DP-28)
400 mil 28-pin plastic SOP (FP-28D)
28-pin plastic TSOP (TFP-28DB)
32-pin plastic TSOP (TFP-32DA)
400 mil 28-pin plastic SOP (FP-28DV)
Lead free
28-pin plastic TSOP (TFP-28DBV)
Lead free
32-pin plastic TSOP (TFP-32DAV)
Lead free
Pin Arrangement
HN58C256AP/AFP Series
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(Top view)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
A10
15
16
17
18
19
20
21
22
23
24
25
26
27
28
(Top view)
HN58C257AT Series
A2
A1
A0
NC
I/O0
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
I/O7
NC
A10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
(Top view)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A4
A5
A6
A7
A12
A14
RDY/
Busy
V
CC
HN58C256AT Series
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A4
A5
A6
A7
A12
A14
V
CC
WE
A13
A8
A9
A11
OE
A10
WE
OE
CE
I/O7
I/O6
I/O5
I/O4
I/O3
CE
A13
A8
A9
A11
RES
WE
A13
A8
A9
A11
CE
OE
Rev.5.00, Nov. 17.2003, page 2 of 23
HN58C256A Series, HN58C257A Series
Pin Description
Pin name
A0 to A14
I/O0 to I/O7
OE
CE
WE
V
CC
V
SS
RDY/Busy*
RES*
NC
Note:
1
1
Function
Address input
Data input/output
Output enable
Chip enable
Write enable
Power supply
Ground
Ready busy
Reset
No connection
1. This function is supported by only the HN58C257A series.
Block Diagram
Note: 1. This function is supported by only the HN58C257A series.
V
CC
V
SS
I/O0
High voltage generator
to
I/O7
RDY/
Busy
*
1
RES
*
1
OE
CE
WE
RES
*
1
A0
to
I/O buffer
and
input latch
Control logic and timing
Y decoder
Y gating
A5
Address
buffer and
latch
A6
to
X decoder
Memory array
A14
Data latch
Rev.5.00, Nov. 17.2003, page 3 of 23
HN58C256A Series, HN58C257A Series
Operation Table
Operation
Read
Standby
Write
Deselect
Write inhibit
Data
polling
Program reset
CE
V
IL
V
IH
V
IL
V
IL
×
×
V
IL
×
OE
V
IL
×*
2
WE
V
IH
×
V
IL
V
IH
V
IH
×
V
IH
×
RES*
RES
V
H
*
×
V
H
V
H
×
×
V
H
V
IL
1
3
RDY/Busy
Busy*
Busy
High-Z
High-Z
3
I/O
Dout
High-Z
Din
High-Z
Dout (I/O7)
High-Z
V
IH
V
IH
×
V
IL
V
IL
×
High-Z to V
OL
High-Z
V
OL
High-Z
Notes: 1. Refer to the recommended DC operating condition.
2.
×
: Don’t care
3. This function is supported by only the HN58C257A series.
Absolute Maximum Ratings
Parameter
Power supply voltage rerative to V
SS
Input voltage rerative to V
SS
Operationg temperature range*
Storage temperature range
2
Symbol
V
CC
Vin
Topr
Tstg
Value
−0.6
to +7.0
−0.5*
to +7.0*
1
3
Unit
V
V
0 to +70
−55
to +125
°
C
°
C
Notes: 1. Vin min =
−3.0
V for pulse width
≤
50 ns
2. Including electrical characteristics and data retention
3. Should not exceed V
CC
+ 1 V.
Recommended DC Operating Conditions
Parameter
Supply voltage
Input voltage
Symbol
V
CC
V
SS
V
IL
V
IH
V
H
*
Operating temperature
3
Min
4.5
0
−0.3*
2.2
V
CC
−0.5
0
1
Typ
5.0
0
Max
5.5
0
0.8
2
Unit
V
V
V
V
V
CC
+ 0.3* V
V
CC
+ 1.0
+70
Topr
°
C
Notes: 1. V
IL
min: –1.0 V for pulse width
≤
50 ns.
2. V
IH
max: V
CC
+ 1.0 V for pulse width
≤
50 ns.
3. This function is supported by only the HN58C257A series.
Rev.5.00, Nov. 17.2003, page 4 of 23
HN58C256A Series, HN58C257A Series
DC Characteristics
(Ta = 0 to +70°C, V
CC
= 5.0 V
±
10%)
Parameter
Input leakage current
Output leakage current
Standby V
CC
current
Operating V
CC
current
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
CC3
Min
Output low voltage
Output high voltage
Note:
V
OL
V
OH
2.4
Typ
Max
2*
2
20
1
12
30
0.4
1
Unit
µA
µA
µA
mA
mA
mA
V
V
Test conditions
V
CC
= 5.5 V, Vin = 5.5 V
V
CC
= 5.5 V, Vout = 5.5/0.4 V
CE
= V
CC
CE
= V
IH
Iout = 0 mA, Duty = 100%,
Cycle = 1
µs,
V
CC
= 5.5 V
Iout = 0 mA, Duty = 100%,
Cycle = 85 ns, V
CC
= 5.5 V
I
OL
= 2.1 mA
I
OH
=
−400 µA
1. I
LI
on
RES
= 100
µA
max (only the HN58C257A series)
Capacitance
(Ta = +25°C, f = 1 MHz)
Parameter
Input capacitance*
Note:
1
1
Symbol
Cin
Cout
Min
Typ
Max
6
12
Unit
pF
pF
Test conditions
Vin = 0 V
Vout = 0 V
Output capacitance*
1. This parameter is periodically sampled and not 100% tested.
Rev.5.00, Nov. 17.2003, page 5 of 23
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
