HD30 ·
HD40
ADP I
SRAM
o
5 Volt x8 Dual-Port Static RAM
Memory Configuration
1K x 8
1K x 8
Device
HD30
HD40
Key Features:
•
•
•
•
•
•
•
•
•
Industry leading Dual-Port Static RAM (up to 15ns)
Simultaneous memory access through two ports
5V power supply
Easily expandable in both word depth and width
Interrupt and Busy Logic
Available packages: 64 – pin Thin Quad Flat Pack (TQFP), 52 – pin Plastic Lead Chip Carrier (PLCC)
(0
°
C to 70
°
C) Commercial operating temperature available for access time of 15ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for access time of 25ns
Pin-to-pin compatible with conventional dual-port devices including IDT (IDT7130, IDT7140) and Cypress
(CY7C130, CY7C140)
Product Description:
HBA’s Asynchronous Dual-Port (ADP) II Static RAM offers industry leading 0.25um process technology and 1K x 8 memory
configuration. The device supports two memory ports with independent control, address, and I/O pins that enable simultaneous,
asynchronous access to any location in memory. System designers have full flexibility of implementing deeper and wider
memory using the depth and width expansion features.
The HD30 is a stand alone 8K-bit Dual-Port Static RAM or as a “MASTER” Dual-Port Static RAM with HD40 as a “SLAVE”
Dual-Port Static RAM in 16-bit-or-more bus width application. No additional discrete logic is required when using the
MASTER/SLAVE configuration to provide bus width expansion.
These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such
as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.
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HD30 ·
HD40
ADP I
SRAM
Block Diagram of Dual-Port Static RAM
1K x 8
OE
L
CE
L
R/ W
L
OE
R
CE
R
R/ W
R
I/O
0-7
L
I/O
Control
(1, 2)
I/O
Control
I/O
0-7
R
BUSY
L
BUSY
R
(1, 2)
A
9
L
A
0
L
Address
Decoder
SRAM
10
10
Address
Decoder
A
9
R
A
0
R
CE
L
OE
L
R/ W
L
Busy Arbitration
and
Interrupt Logic
CE
R
OE
R
R/ W
R
INT
L
(2)
INT
R
(2)
NOTES:
1.
2.
HD30 (MASTER): BUSY is open drain. HD40 (SLAVE): BUSY is input
Open drain output: requires pull-up resistor of 270Ω
Figure 2. Device Architecture
__________
__________
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HD30 ·
HD40
ADP I
SRAM
BUSY
L
BUSY
R
R/W
L
R/W
R
INT
L
NC
NC
NC
Vcc
CE
R
CE
L
Vcc
INT
R
NC
NC
50
Index
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
A
7L
A
8L
A
9L
NC
I/O
0L
I/O
1L
I/O
2L
49
NC
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
48
47
46
45
44
43
42
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
NC
A
7R
A
8R
A
9R
NC
NC
I/O
7R
I/O
6R
TQFP - 64 (Drw No: PF-01A; Order code: PF)
Top View
41
40
39
38
37
36
35
34
33
GND
GND
I/O
3L
NC
NC
I/O
0R
I/O
1R
I/O
2R
I/O
3R
NC
I/O
4R
R/W
R
BUSY
R
BUSY
L
R/W
L
INT
L
OE
L
CE
L
A
0L
NC
INT
R
48
Vcc
CE
R
Index
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
6
5
4
3
2
1
52
51
50
49
NC
47
46
45
44
43
42
41
I/O
5R
I/O
4L
I/O
5L
I/O
6L
I/O
7L
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
PLCC - 52 (Drw No: J-01A; Order code: J)
Top View
40
39
38
37
36
35
34
22
23
24
25
26
27
28
29
30
31
32
33
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
Figure 3. Device Pin-Out
I/O
6R
I/O
4L
I/O
5L
I/O
6L
I/O
7L
NC
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HD30 ·
HD40
ADP I
SRAM
Left Port
_____
Right Port
CE
R
BUSY
R
INT
R
OE
R
A
0R-9R
I/O
0R –7R
Vcc
_____
______
__________
_____
Name
Chip Enable
Read / Write Enable
Busy Flag
Interrupt Flag
Output Enable
Address
Data Inputs/Outputs
Power
Ground
Symbol
Rating
Terminal Voltage with
respect to GND
Temperature Under Bias
Storage Temperature
DC Output Current
Com & Ind
-0.5 to + 7.0
-55 to +125
-65 to +150
50
Unit
V
°
CE
L
BUSY
L
INT
L
OE
L
A
0L-9L
I/O
0L-7R
GND
_____
______
__________
R/W
L
____
R/W
R
____
V
TERM
T
BIAS
T
STG
I
OUT
NOTES:
C
C
°
mA
Table 1. Pin Descriptions
Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended
period of operation is outside this range. Standard operation should fall within the Recommended
Operating Conditions
.
Table 2. Absolute Maximum Ratings
Commercial Clock
Symbol
Parameter
Recommended Operating Conditions
Min.
4.5
0
2.2
-0.5
0
-
-
2.4
-
Industrial Clock
Min.
4.5
0
2.2
-0.5
-40
-
-
2.4
-
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
6.0
0.8
70
10
10
-
0.4
Typ.
5.0
0
-
-
-
-
-
-
-
Max.
5.5
0
6.0
0.8
85
10
10
-
0.4
Unit
V
V
V
V
°
V
CC
GND
Supply Voltage Com’l/Ind’l
Supply Voltage
Input High Voltage Com’l/Ind’l
Input Low Voltage Com’l/Ind’l
Operating Temperature
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, IOH = -4mA
Output Logic “0” Voltage, IOL = 4mA,
IOL=16mA
(1)
V
IH
V
IL
T
A
I
LI
I
LO
V
OH
V
OL
C
DC Electrical Characteristics
µA
µA
V
V
Capacitance at 1.0MHz Ambient Temperature (25°C)
Parameter
(2)
Symbol
Input Capacitance
C
IN
Output Capacitance
C
OUT
NOTES:
__________
______
Conditions
V
IN
= 3dV
(3)
V
OUT
= 3dV
(3)
Max.
9
10
Unit
pF
pF
1. B U S Y and INT pins only.
2. This parameter is guaranteed but not tested.
3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V.
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HD30 ·
HD40
ADP I
SRAM
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD30L15
HD40L15
Typ.
Max.
190
-
75
-
135
-
5
-
125
-
110
-
30
-
65
-
0.2
-
60
-
HD30L25
HD40L25
Typ.
110
30
65
Unit
Max.
170
45
115
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
0.2
5
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
60
105
mA
Power Consumption
Symbol
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current (Both
Ports – TTL Level
Inputs)
Standby Current (One
Port – TTL Level Inputs)
Full Standby Current
(Both Ports – All CMOS
Level Inputs)
Standby Current (One
Port – All CMOS Level
Inputs)
NOTES:
1.
2.
3.
4.
At f=f
MAX
, address and control lines, except Output Enable, are cycling at the maximum frequency read cycle of 1/trc, and using AC Test Conditions of input level of GND
to 3V.
f = 0 means no address or control lines change.
Vcc = 5V, tA = +25C for Typ and is not production tested. Vcc dc = 100mA (Typ)
Port A and B can be either left or right port. If Port A is left port, Port B is right port. If Port A is right port, Port B is left port.
_____
Conditions
CE = V
IL
, Outputs Disabled,
f=f
MAX
_____
Temp
C
I
C
I
C
I
C
I
C
I
HD30L35
HD40L35
Typ.
Max.
120
-
45
-
90
-
4
-
85
-
80
-
25
-
50
-
0.2
-
45
-
HD30L55
HD40L55
Typ.
65
-
20
-
40
-
0.2
-
40
-
Unit
Max.
90
-
35
-
75
-
4
mA
-
70
-
mA
mA
mA
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
CE
L
= CE
R
= V
IH
, f=f
MAX
CE
A
= V
IL
and CE
B
= V
IH
Active Port Outputs Disabled,
f=f
MAX
Both Ports CE
L
and CE
R
> Vcc
– 0.2V, V
IN
> Vcc – 0.2V or
V
IN
< 0.2V, f = 0
_____
_____
_____
_____
_____
mA
CE
A
< 0.2V and CE
B
> Vcc –
0.2V, Active Port Outputs
Disabled, f=f
MAX
_____
_____
5HD087
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