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IS62WV12816BLL-55B2I

产品描述128KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, MO-207, TFBGA-48
产品类别存储    存储   
文件大小191KB,共17页
制造商ABLIC
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IS62WV12816BLL-55B2I概述

128KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, MO-207, TFBGA-48

IS62WV12816BLL-55B2I规格参数

参数名称属性值
厂商名称ABLIC
零件包装代码DSBGA
包装说明TFBGA,
针数48
Reach Compliance Codeunknown
最长访问时间55 ns
JESD-30 代码R-PBGA-B48
长度8 mm
内存密度2097152 bit
内存集成电路类型STANDARD SRAM
内存宽度16
功能数量1
端子数量48
字数131072 words
字数代码128000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织128KX16
封装主体材料PLASTIC/EPOXY
封装代码TFBGA
封装形状RECTANGULAR
封装形式GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.5 V
标称供电电压 (Vsup)3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式BALL
端子节距0.75 mm
端子位置BOTTOM
宽度6 mm
Base Number Matches1

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IS62WV12816ALL
IS62WV12816BLL
128K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns, 55ns, 70ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
– 1.65V--2.2V V
DD
(62WV12816ALL)
– 2.5V--3.6V V
DD
(62WV12816BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• 2CS Option Available
• Lead-free available
JANUARY 2010
DESCRIPTION
The
ISSI
IS62WV12816ALL/ IS62WV12816BLL are high-
speed, 2M bit static RAMs organized as 128K words by 16
bits. It is fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1
is LOW, CS2 is HIGH and both
LB
and
UB
are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory. A
data byte allows Upper Byte
(UB)
and Lower Byte (LB)
access.
The IS62WV12816ALL and IS62WV12816BLL are packaged
in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and
44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. H
01/13/2010
1

 
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