DATASHEET
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
Description
The ICS308 is a versatile serially programmable, quad
PLL clock source. The ICS308 can generate any
frequency from 250 kHz to 200 MHz, and up to 6
different output frequencies simultaneously. The
outputs can be reprogrammed on the fly, and will lock to
a new frequency in 10 ms or less. Smooth transitions
(in which the clock duty cycle remains roughly 50%) are
guaranteed if the output divider is not changed.
The device includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS308 default for non-programmed start-up are
buffered reference clock outputs on all clock output
pins.
ICS308
Features
•
Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS
compliant
•
Operating voltage of 3.3 V
•
Highly accurate frequency generation
•
M/N Multiplier PLL: M = 1..2048, N = 1..1024
•
Serially programmable: user determines the output
frequency via a 3-wire interface
•
Eliminates need for custom quartz oscillators
•
Input crystal frequency of 5 - 27 MHz
•
Optional programmable on-chip crystal capacitors
•
Output clock frequencies up to 200 MHz
•
Reference clock output
•
Power down tri-state mode
•
Very low jitter
Block Diagram
V DD
3
CLK1
P LL1
CLK2
Divide
Logic
and
Output
Enable
Control
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
STROBE
SCLK
DATA
P LL3
C rystal or
clock input
X 1/IC LK
C rystal
O scillator
X2
GND
2
P D TS
P LL4
P LL2
E xternal capacitors are
required w ith a crystal input.
IDT™ / ICS™
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 1
ICS308
REV L 051310
ICS308
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
SER PROG CLOCK SYNTHESIZER
Pin Assignment
D AT A
X2
X1/IC LK
C LK9
VDD
GND
C LK1
C LK2
C LK3
C LK4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ST R O BE
SC LK
PD T S
VD D
VD D
GND
C LK5
C LK6
C LK7
C LK8
20 pin (150 m il) SSOP (QSOP)
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
DATA
X2
X1/ICLK
CLK9
VDD
GND
CLK1
CLK2
CLK3
CLK4
CLK8
CLK7
CLK6
CLK5
GND
VDD
VDD
PDTS
SCLK
STROBE
Pin
Type
Input
XO
XI
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Input
Input
Input
Serial data input.
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect this pin to a crystal or external clock input.
Output clock 9. Default of Reference frequency output when unprogrammed.
Connect to +3.3 V.
Connect to Ground.
Output clock 1. Default of Reference frequency output when unprogrammed.
Output clock 2. Default of Reference frequency output when unprogrammed.
Output clock 3. Default of Reference frequency output when unprogrammed.
Output clock 4. Default of Reference frequency output when unprogrammed.
Output clock 8. Default of Reference frequency output when unprogrammed.
Output clock 7. Default of Reference frequency output when unprogrammed.
Output clock 6. Default of Reference frequency output when unprogrammed.
Output clock 5. Default of Reference frequency output when unprogrammed.
Connect to Ground.
Connect to +3.3 V.
Connect to +3.3 V.
Powers down entire chip, tri-states all outputs when low. Internal pull-up.
Serial Shift register clock. See timing diagram.
Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.
Pin Description
IDT™ / ICS™
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 2
ICS308
REV L 051310
ICS308
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
SER PROG CLOCK SYNTHESIZER
Configuring the ICS308
Initial State: The ICS308 may be configured to have up to nine frequency outputs, utilizing the four
on-board PLLs. Unprogrammed, the part has the following outputs, related to the reference input clock:
Default Outputs
Output
Clock 1-9 (Pins 4, 10 - 14)
Frequency
Reference Output
The STROBE pin must have an external 250 kOhm pull-up resistor to achieve the Initial State.
The input crystal range for the ICS308 is 5 MHz to 27 MHz.
The ICS308 can be programmed to set the output functions and frequencies. 160 data bits generated by
the VersaClock
TM
software are written in DATA pin in this order: MSB (left most bit) first.
As show in Figure 2, after these 160 bits are clocked into the ICS308, taking STROBE high will send this
data to the internal hatch and the CLK output will lock within 10 ms.
Note:
STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high
state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will
change accordingly. Although this will not damage the ICS308, it is recommended that STROBE be kept
low while DATA is being clocked into the ICS308 in order to avoid unintended changes on the output clocks.
All outputs may be turned off during initialization by bringing the PDTS pin to Ground. When PDTS is
brought high, after the Strobe pin in brought high, the programmed output frequencies will be available.
AC Parameters for Writing to the ICS308
Parameter
t
SETUP
t
HOLD
t
W
t
S
Condition
Setup time
Hold time after SCLK
Data wait time
Strobe pulse width
SCLK Frequency
Min.
10
10
10
40
30
Max.
Units
ns
ns
ns
ns
MHz
DATA
t
setup
Bit160
Bit159
Bit158
t
hold
Bit3
Bit2
Bit1
SCLK
t
w
STROBE
t
s
Figure 2. Tim ing Diagram for Program m ing the ICS308
IDT™ / ICS™
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 3
ICS308
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ICS308
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
SER PROG CLOCK SYNTHESIZER
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to each clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.
STROBE Pull-up Resistor
In order for the device to start up in the default state, a
250 kOhm pull-up resistor is required.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS308 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
ICS308 Configuration Capabilities
The architecture of the ICS308 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS308 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
Output Freq. = (Ref. Freq)*(M/N)/Output Divide
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors must
be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal (C
L
-6 pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 20 pF
[(16-6) x 2 = 20].
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
IDT™ / ICS™
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 4
ICS308
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ICS308
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
SER PROG CLOCK SYNTHESIZER
VersaClock Software
IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target
reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with
only a press of a button. The user does not need to have prior PLL experience or determine the optimal
VCO frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and
provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in seconds.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS308. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Item
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD+ 0.5
VDD+ 0.5
150
260
Units
V
V
V
°
C
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS308R)
Ambient Operating Temperature (ICS308RI)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.0
Typ.
Max.
+70
+85
+3.6
4
Units
°
C
°
C
V
ms
IDT™ / ICS™
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 5
ICS308
REV L 051310
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