PRELIMINARY
CY24119
MediaClock™ 27-MHz VCXO Clock Generator
Features
• Low-jitter, high-accuracy output
• VCXO with analog adjust
• 3.3V operation
Part Number
CY24119
Outputs
1
Input Frequency Range
27-MHz pullable crystal per
Cypress Specification
Output Frequencies
One copy of 27 MHz (3.3V)
Benefits
Meets critical timing requirements in complex system designs
Large ± 150 ppm range, better linearity
Logic Block Diagram
27 XIN
OSC
XOUT
27 MHz
Pin Configuration
CY24119
8-pin SOIC
XIN
AVDD
VCXO
AVSS
1
2
3
4
8
7
6
5
XOUT
VSS
27 MHz
VDD
VCXO
AVDD VDD
AVSS
VSS
Cypress Semiconductor Corporation
Document #: 38-07200 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 13, 2002
PRELIMINARY
Pin Summary
Name
A
VDD
V
DD
AV
SS
V
SS
X
IN
V
CXO
X
OUT
27 MHz
Pin Number
2
5
4
7
1
3
8
6
Description
Analog Voltage Supply
Output Voltage Supply
Analog Ground
Output Ground
Reference Crystal Input
Analog Control for V
CXO
Reference Crystal Output
27-MHz Clock Output
CY24119
Absolute Maximum Conditions
Parameter
V
DD
T
S
T
J
Description
Supply Voltage
Storage Temperature
[1]
Min.
–0.5
–65
2
Max.
7.0
125
125
Unit
V
°C
°C
kV
Junction Temperature
Electrostatic Discharge
Recommended Operating Conditions
Parameter
V
DD
, AV
DD
T
A
C
LOAD
f
REF
Description
Operating Voltage
Ambient Temperature
Max Load Capacitance
Reference Frequency
10
27
Min.
3.14
0
Typ.
3.3
Max.
3.47
70
15
30
Unit
V
°C
pF
MHz
DC Electrical Characteristics
Parameter
I
OH
I
OL
C
IN
I
IZ
Name
Output HIGH Current
Output LOW Current
Input Capacitance
Input Leakage Current
V
CXO
Pullability Range
V
CXO
Input Range
V
CXO
Input Bandwidth
Supply Current
Sum of Core and Output Current
–150
0
DC to 200
13
5
+150
AV
DD
Description
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
Min.
12
12
Typ.
24
24
7
Max.
Unit
mA
mA
pF
µA
ppm
V
kHz
mA
f
∆
xo
V
VCXO
f
VBW
I
DD
Pullable Crystal Specifications
Parameter
CR
load
C0/C1
ESR
T
o
Crystal Accuracy
TT
s
Notes:
1. Rated for 10 years.
Name
Crystal Load Capacitance
Equivalent Series Resistance
Operating Temperature
Crystal Accuracy
Stability over Temperature and
Aging
0
Min.
13
Typ.
240
35
50
70
+20
+20
+50
Max.
pF
Ω
°C
Unit
ppm
ppm
Document #: 38-07200 Rev. **
Page 2 of 5
PRELIMINARY
AC Electrical Characteristics
(V
DD
= 3.3V)
Parameter
[2]
DC
t
3
t
4
t
9
Name
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Clock Jitter
Description
Duty Cycle is defined in
Figure 1,
50% of V
DD
Output Clock Rise Time, 20% – 80% of V
DD
Output Clock Fall Time, 80% – 20% of V
DD
Peak-to-Peak Period Jitter
Min.
45
0.8
0.8
Typ.
50
1.4
1.4
CY24119
Max.
55
Unit
%
V/ns
V/ns
100
ps
t1
t2
27 MHz
50%
27 MHz
t3
80%
20%
t4
Figure 1. Duty Cycle Definition; DC = t
2
/t
1
Figure 2. Rise and Fall Time Definitions
AV
DD
0.1
µ
F
OUTPUTS
CLK out
C
LOAD
V
DD
0.1
µ
F
GND
Test Circuit
Ordering Information
Ordering Code
CY24119-SC
CY24119-SCT
Note:
2. Not 100% tested.
Package
Name
S8
S8
Package Type
8-pin SOIC
8-pin SOIC – Tape and Reel
Operating Range
Commercial
Commercial
Operating Voltage
3.3V
3.3V
Document #: 38-07200 Rev. **
Page 3 of 5
PRELIMINARY
Package Diagram
8-lead (150-mil) SOIC S8
CY24119
51-85066-A
MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the
trademarks of their respective holders.
Document #: 38-07200 Rev. **
Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
Document Title: CY24119 MediaClock™ 27-MHz VCXO Clock Generator
Document Number: 38-07200
REV.
**
ECN NO.
111551
Issue
Date
03/22/02
Orig. of
Change
CKN
New Data Sheet
Description of Change
CY24119
Document #: 38-07200 Rev. **
Page 5 of 5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
