LT1166
Power Output Stage
Automatic Bias System
FEATURES
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DESCRIPTION
The LT
®
1166 is a bias generating system for controlling
class AB output current in high powered amplifiers. When
connected with external transistors, the circuit becomes a
unity-gain voltage follower. The LT1166 is ideally suited
for driving power MOSFET devices because it eliminates
all quiescent current adjustments and critical transistor
matching. Multiple output stages using the LT1166 can be
paralleled to obtain higher output current.
Thermal runaway of the quiescent point is eliminated
because the bias system senses the current in each power
transistor by using a small external sense resistor. A high
speed regulator loop controls the amount of drive applied
to each power device. The LT1166 can be biased from a pair
of resistors or current sources and because it operates on the
drive voltage to the output transistors, it operates on any
supply voltage.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Set Class AB Bias Currents
Eliminates Adjustments
Eliminates Thermal Runaway of I
Q
Corrects for Device Mismatch
Simplifies Heat Sinking
Programmable Current Limit
May Be Paralleled for Higher Current
Small SO-8 or PDIP Package
APPLICATIONS
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s
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Biasing Power MOSFETs
High Voltage Amplifiers
Shaker Table Amplifiers
Audio Power Amplifiers
TYPICAL APPLICATION
R1
MPS2907
100Ω
2N2907
1 I
TOP
= 15mA
5.6k
V
TOP
SENSE
+
I
LIM+
4.3k
V
IN
2
8
7
1k
1µF
V
IN
LT1166 V
OUT
I
LIM–
3
1µF
1k
R
SENSE+
0.33Ω
V
OUT
R
SENSE–
0.33Ω
1Ω
47Ω
15V
R2
100Ω
IRF530
300pF
Unity Gain Buffer Amp Driving 1Ω Load
+
220µF
INPUT
6
5
SENSE
–
V
BOTTOM
4 I
BOTTOM
= 15mA
2N2222
R4
100Ω
MPS2222
47Ω
R3
100Ω
300pF
–15V
OUTPUT
IRF9530
1166 • TA01
220µF
1166 • F01
Figure 1. Unity Gain Buffer with Current Limit
U
+
U
U
0V
0V
1
LT1166
ABSOLUTE
MAXIMUM
RATINGS
Supply Current (Pin 1 or Pin 4) ............................ 75mA
Differential Voltage (Pin 2 to Pin 3) .........................
±6V
Output Short-Circuit Duration (Note 1) ......... Continuous
Specified Temperature Range (Note 2) ........ 0°C to 70°C
Operating Temperature Range ................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Junction Temperature (Note 3) ............................ 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
PACKAGE/ORDER INFORMATION
TOP VIEW
V
TOP
1
V
IN
2
V
OUT
3
V
BOTTOM
4
N8 PACKAGE
8-LEAD PDIP
+1
8
7
6
5
SENSE
+
I
LIM +
I
LIM
–
ORDER PART
NUMBER
LT1166CN8
LT1166CS8
S8 PART MARKING
1166
SENSE
–
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C,
θ
JA
= 100°C/ W (N8)
T
JMAX
= 150°C,
θ
JA
= 150°C/ W (S8)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
Pin 1 = 2V, Pin 4 = – 2V, Operating current 15mA and R
IN
= 20k, unless otherwise specified.
PARAMETER
Output Offset Voltage
Input Bias Current
Input Resistance
V
AB
(Top)
V
AB
(Bottom)
Voltage Compliance
Current Compliance
Transconductance
gm
CC2
gm
EE2
gm
CC10
gm
EE10
PSRR
CC
PSRR
EE
Current Limit Voltage
CONDITIONS
Operating Current 15mA to 50mA
Operating Current 15mA to 50mA (Note 4)
Operating Current 15mA to 50mA (Note 5)
Measure Pin 8 to Pin 3, No Load
Measure Pin 5 to Pin 3, No Load
Operating Current = 50mA (Notes 6, 9)
Operating Voltage =
±2V
(Note 7)
Pin 1 = 2V, Pin 4 = – 2V
Pin 1 = 2V, Pin 4 = – 2V
Pin 1 = 10V, Pin 4 = – 10V
Pin 1 = 10V, Pin 4 = – 10V
(Note 8)
(Note 8)
Operating Current 15mA to 50mA
Pin 7 Voltage to Pin 3
Pin 6 Voltage to Pin 3
MIN
q
q
q
q
q
q
q
q
q
2
14
– 14
±2
±4
0.08
0.08
0.09
0.09
TYP
50
2
15
20
– 20
MAX
250
10
26
– 26
±10
±50
0.13
0.13
0.16
0.16
UNITS
mV
µA
MΩ
mV
mV
V
mA
mho
mho
mho
mho
dB
dB
V
V
0.100
0.100
0.125
0.125
19
19
1.3
– 1.3
q
q
1.0
– 1.0
1.5
– 1.5
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
External power devices may require heat sinking.
Note 2:
Commercial grade parts are designed to operate over the
temperature range of – 40°C to 85°C but are neither tested nor guaranteed
beyond 0°C to 70°C. Industrial grade parts specified and tested over
– 40°C and 85°C are available on special request, consult factory.
Note 3:
T
J
calculated from the ambient temperature T
A
and the power
dissipation P
D
according to the following formulas:
LT1166CN8: T
J
= T
A
+ (P
D
• 100°C/W)
LT1166CS8: T
J
= T
A
+ (P
D
• 150°C/W)
Note 4:
I
TOP
= I
BOTTOM
Note 5:
The input resistance is typically 15MΩ when the loop is closed.
When the loop is open (current limit) the input resistance drops to 200Ω
referred to Pin 3.
Note 6:
Maximum T
J
can be exceeded with 50mA operating current and
simultaneous 10V and – 10V (20V total).
Note 7:
Apply
±200mV
to Pin 2 and measure current change in Pin 1
and 4. Pin 3 is grounded.
Note 8:
PSRR
CC
= gm
CC2
– gm
CC10
gm
CC2
PSRR
EE
= gm
EE2
– gm
EE10
gm
EE2
Note 9:
For Linear Operation, Pin 1 must not be less than 2V or more than
10V from Pin 3. Similarly, Pin 4 must not be less than 2V or more than
10V from Pin 3.
2
U
W
U
U
W W
W
LT1166
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current vs
Current Source Mismatch
150
OUTPUT OFFSET VOLTAGE (mV)
100
INPUT BIAS CURRENT (µA)
50
0
–50
–100
I
TOP
= I
BOTTOM
= 50mA
400
200
0
–200
–400
–600
R
IN
= 20k
OUTPUT OFFSET VOLTAGE (mV)
I
TOP
= I
BOTTOM
= 4mA
–150
2.5 5.0 7.5
–10 –7.5 –5.0 –2.5 0
CURRENT SOURCE MISMATCH (%)
Input Bias Current vs
Temperature
3.0
2.9
INPUT BIAS CURRENT (µA)
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
–50 –25
OUTPUT VOLTAGE SWING (V)
R
L
=
∞
I
TOP
= I
BOTTOM
= 15mA
R
IN
= 4.3k
0
–2
–4
–6
–8
R
TOP
= R
BOTTOM
= 1k
GAIN (dB)
50
25
0
75
TEMPERATURE (°C)
Closed-Loop Voltage Gain vs
Frequency
VOLTAGE DROP ACROSS SENSE RESISTORS (mV)
I
LIM
PIN VOLTAGE REFERENCED TO V
OUT
(V)
2
1
0
–1
GAIN (dB)
R
L
=
∞
R
L
=10Ω
–2
–3
–4
–5
–6
–7
V
S
=
±15V
R
IN
= 4.3k
I
TOP
= I
BOTTOM
= 12mA
C
1
= C
2
= 500pF
SEE FIGURE 8
0.01
0.1
1
FREQUENCY (MHz)
10
LT1166 • TPC07
–8
0.001
U W
LT1166 • TPC01
Output Offset Voltage vs
Current Source Mismatch
800
600
I
TOP
= I
BOTTOM
= 50mA
55
50
45
40
35
60
Output Offset Voltage vs
Temperature
R
L
=
∞
I
TOP
= I
BOTTOM
= 15mA
R
IN
= 4.3k
R
IN
= 2k
10
–800
–1.0 –0.75 –0.5 –0.25 0 0.25 0.5 0.75 1.0
I
TOP
AND I
BOTTOM
MISMATCH (mA)
LT1166 • TPC02
30
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
LT1166 • TPC03
Output Voltage vs Input Voltage
10
8
6
4
2
R
IN
= 4.3k
C
1
= C
2
= 500pF
R
L
= 10Ω
SEE FIGURE 8
30
25
20
15
10
5
0
–5
–10
–15
Open-Loop Voltage Gain vs
Frequency
R
L
=
∞
R
L
=10Ω
I
TOP
= I
BOTTOM
= 12mA
V
S
=
±15V
R
IN
= 4.3k
I
TOP
= I
BOTTOM
= 12mA
C
1
= C
2
= 500pF
SEE FIGURE 8
0.01
0.1
1
FREQUENCY (MHz)
10
LT1166 • TPC06
100
125
–10
–10 –8 –6 –4 –2 0 2 4
INPUT VOLTAGE (V)
6
8
10
–20
0.001
LT1166 • TPC04
LT1166 • TPC05
Voltage Across Sense Resistors
vs Temperature
24
22
20
18
16
SENSE
+
1.25
Current Limit Pin Voltage vs
Temperature
V
IN
=
±1.5V
1.20
PIN 7 TO PIN 3
1.15
–16
–18
–20
–22
–24
–50 –25
SENSE
–
50
25
0
75
TEMPERATURE (°C)
100
125
–1.15
–1.20
PIN 6 TO PIN 3
–1.25
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LT1166 • TPC08
LT1166 • TPC09
3
LT1166
TYPICAL PERFORMANCE CHARACTERISTICS
Input Transconductance vs
Supply Voltage
0.120
INPUT TRANSCONDUCTANCE (mhos)
10
25°C
125°C
– 55°C
gm
CC
0.100
0.090
0.080
TOTAL HARMONIC DISTORTION (%)
0.110
R
L
= 10Ω
P
O
= 1W
SEE FIGURE 8
1
SENSE PIN VOLTAGE REFERENCED TO V
OUT
(mV)
–0.080
–0.090
–0.100
–0.110
–0.120
0
25°C
125°C
– 55°C
V
IN
=
±200mV
R
L
= 0
R
IN
= 0
gm
EE
1
2
3 4 5 6 7 8
SUPPLY VOLTAGE (V)
PIN FUNCTIONS
V
TOP
(Pin 1):
Pin 1 establishes the top side drive voltage
for the output transistors. Operating supply current enters
Pin 1 and a portion biases internal circuitry; Pin 1 current
should be greater than 4mA. Pin 1 voltage is internally
clamped to 12V with respect to V
OUT
and the pin current
should be limited to 75mA maximum.
V
IN
(Pin 2):
Pin 2 is the input to a unity gain buffer which
drives V
OUT
(Pin 3). During a fault condition (short circuit)
the input impedance drops to 200Ω and the input current
must be limited to 5mA or V
IN
to V
OUT
limited to less than
±6V.
V
OUT
(Pin 3):
Pin 3 of the LT1166 is the output of a voltage
control loop that maintains the output voltage at the input
voltage.
V
BOTTOM
(Pin 4):
Pin 4 establishes the bottom side drive
voltage for the output transistors. Operating supply cur-
rent exits this pin; Pin 4 current should be greater than
4mA. Pin 4 voltage is internally clamped to – 12V with
respect to V
OUT
and the pin current should be limited to
75mA maximum.
SENSE
–
(Pin 5):
The Sense
–
pin voltage is established
by the current control loop and it controls the output
quiescent current in the bottom side power device. Limit
the maximum differential voltage between Pin 5 and Pin 3
to
±6V
during fault conditions.
I
LIM –
(Pin 6):
The negative side current limit, limits the
voltage at V
BOTTOM
to V
OUT
during a negative fault condi-
tion. The maximum reverse voltage on Pin 6 with respect
to V
OUT
is 6V.
I
LIM +
(Pin 7):
The positive side current limit, limits the
voltage at V
TOP
to V
OUT
during a positive fault condition.
The maximum reverse voltage on Pin 7 with respect to
V
OUT
is – 6V.
SENSE
+
(Pin 8):
The Sense
+
pin voltage is established by
the current control loop and it controls the output quies-
cent current in the top side power device. Limit the
maximum differential voltage between Pin 8 and Pin 3 to
±6V
during fault conditions.
4
U W
9
Total Harmonic Distortion vs
Frequency
1000
Sense Pin Voltage Referenced to
V
OUT
vs Load Current
V
BOTTOM
V
TOP
100
0.1
10
R
SENSE
= 100Ω
1
10
8
6 4 2
SINKING
0
2
4 6 8
SOURCING
10
10
0.01
0.01
0.1
1
10
FREQUENCY (kHz)
100
LT1166 • TPC11
LT1166 • TPC10
LOAD CURRENT (mA)
LT1166 • TPC12
U
U
U
LT1166
APPLICATIONS INFORMATION
Overvoltage Protection
The supplies V
TOP
(Pin 1) and V
BOTTOM
(Pin 4) have clamp
diodes that turn on when they exceed
±12V.
These diodes
act as ESD protection and serve to protect the LT1166
when used with large power MOS devices that produce
high V
GS
voltage. Current into Pin 1 or Pin 4 should be
limited to
±75mA
maximum.
Multiplier Operation
Figure 2 shows the current multiplier circuit internal to the
LT1166 and how it works in conjunction with power
output transistors. The supply voltages V
T
(top) and V
B
(bottom) of the LT1166 are set by the required “on”
voltage of the power devices. A reference current I
REF
sets
a constant V
BE7
and V
BE8
. This voltage is across emitter
base of Q9 and Q10 which are 1/10 the emitter area of Q7
and Q8. The expression for this current multiplier is:
V
BE7
+ V
BE8
= V
BE9
+ V
BE10
or in terms of current:
(I
C9
)(I
C10
) = (I
REF
)
2
/100 = Constant
The product of I
C9
and I
C10
is constant. These currents are
mirrored and set the voltage on the (+) inputs of a pair of
R
T
1k
1
V
+
V
TOP
I
REF
SHUNT
REGULATOR
Q7
×
10
Q8
×
10
Q9
×
1
Q10
×
1
+
–
V
BOTTOM
R
B
1k
Figure 2. Constant Product Generator
–
I
REF
10
V
AB+
1Ω
1k
3
1k
V
AB–
1Ω
5
V
O
4
U
8
W
+
U
U
internal op amps. The feedback of the op amps force the
same voltage on the (–) inputs and these voltages then
appear on the sense resistors in series with the power
devices. The product of the two currents in the power
devices is constant, as one increases the other decreases.
The excellent logging nature of Q9 and Q10 allows this
relation to hold over many decades in current.
The total current in Q7 and Q8 is actually the sum of I
REF
and a small error current from the shunt regulator. During
high output current conditions the error current from the
regulator decreases. Current conducted by the regulator
also decreases allowing V
T
or V
B
to increase by an amount
needed to drive the power devices.
Driving the Input Stage
Figure 3 shows the input transconductance stage of the
LT1166 that provides a way to drive V
T
and V
B
. When a
positive voltage V
IN
is applied to R
IN
, a small input current
flows into R2 and the emitter of Q2. This effect causes V
O
to follow V
IN
within the gain error of the amplifier. The
input current is then mirrored by Q3/Q4 and current
supplied to Q4’s collector is sourced by power device M1.
The signal current in Q4’s emitter is absorbed by external
resistor R
B
and this causes V
B
to rise by the same amount
R
T
1k
1
V
+
M
1
V
TOP
Q6
×
32
C
EXT1
Q1
Q5
×
1
M
1
1Ω
R
IN
2
R2
V
IN
Q2
Q12
1Ω
R1
Q11
3
V
O
Q4
×
32
Q3
×
1
4
V
BOTTOM
M
2
R
B
1k
V
–
1166 • F03
M
2
C
EXT2
V
–
1166 • F02
Figure 3. Input Stage Driving Gates
5
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