LT1169
Dual Low Noise,
Picoampere Bias Current,
JFET Input Op Amp
FEATURES
s
s
s
s
s
s
s
s
s
s
DESCRIPTIO
Input Bias Current, Warmed Up: 20pA Max
100% Tested Low Voltage Noise: 8nV/√Hz Max
S8 and N8 Package Standard Pinout
Very Low Input Capacitance: 1.5pF
Voltage Gain: 1.2 Million Min
Offset Voltage: 2mV Max
Input Resistance: 10
13
Ω
Gain-Bandwidth Product: 5.3MHz Typ
Guaranteed Specifications with
±5V
Supplies
Guaranteed Matching Specifications
APPLICATI
s
s
s
s
S
s
s
Photocurrent Amplifiers
Hydrophone Amplifiers
High Sensitivity Piezoelectric Accelerometers
Low Voltage and Current Noise Instrumentation
Amplifier Front Ends
Two and Three Op Amp Instrumentation Amplifiers
Active Filters
The LT1169 achieves a new standard of excellence in noise
performance for a dual JFET op amp. For the first time low
voltage noise (6nV/√Hz) is simultaneously offered with
extremely low current noise (1fA/√Hz), providing the low-
est total noise for high impedance transducer applications.
Unlike most JFET op amps, the very low input bias current
(5pA Typ) is maintained over the entire common mode
range which results in an extremely high input resistance
(10
13
Ω).
When combined with a very low input capaci-
tance (1.5pF) an extremely high input impedance results,
making the LT1169 the first choice for amplifying low level
signals from high impedance transducers. The low input
capacitance also assures high gain linearity when buffering
AC signals from high impedance transducers.
The LT1169 is unconditionally stable for gains of 1 or more,
even with 1000pF capacitive loads. Other key features are
0.6mV V
OS
and a voltage gain over 4 million. Each indi-
vidual amplifier is 100% tested for voltage noise, slew rate
(4.2V/µs), and gain-bandwidth product (5.3MHz).
The LT1169 is offered in the S8 and N8 packages.
A full set of matching specifications are provided for
precision instrumentation amplifier front ends. Specifica-
tions at
±5V
supply operation are also provided. For an
even lower voltage noise please see the LT1113 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
Low Noise Light Sensor with DC Servo
C1
2pF
TOTAL 1kHz VOLTAGE NOISE DENSITY (nV/
√Hz)
10k
D2
1N914
C
D
D1
1N914
2N3904
HAMAMATSU
S1336-5BK
(908) 231-0960
V–
R5
10k
R4
1k
R3
1k
7
1/2 LT1169
5
4
–V
R2C2 > C1R1
C
D
= PARASITIC PHOTODIODE CAPACITANCE
V
OUT
= 100mV/µWATT FOR 200nm WAVE LENGTH
330mV/µWATT FOR 633nm WAVE LENGTH
–
+
+
3
–
2
R1
1M
1
C2
0.022µF
+V
8
V
OUT
1k
1/2 LT1169
100
6
R2
100k
10
1
100
LT1169 • TA01
U
1kHz Output Voltage Noise
Density vs Source Resistance
–
+
R
SOURCE
V
N
UO
UO
V
N
SOURCE
RESISTANCE
ONLY
1k
T
A
= 25°C
V
S
= ±15V
10k 100k 1M 10M 100M 1G
SOURCE RESISTANCE (Ω)
V
N
=
√
(V
OP AMP
)
2
+ 4kTR
S
+ 2qI
B
R
S2
LT1169 • TA02
1
LT1169
ABSOLUTE
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
OUT A 1
–IN A 2
+IN A 3
V
–
4
N8 PACKAGE
8-LEAD PDIP
A
B
Supply Voltage
– 55°C to 105°C ...............................................
±20V
105°C to 125°C ...............................................
±16V
Differential Input Voltage ......................................
±40V
Input Voltage (Equal to Supply Voltage) ...............
±20V
Output Short-Circuit Duration......................... Indefinite
Operating Temperature Range ............... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................ 300°C
8 V
+
7 OUT B
6 –IN B
5 +IN B
ORDER PART
NUMBER
LT1169CN8
LT1169CS8
S8 PART MARKING
1169
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C,
θ
JA
= 80°C/W (N8)
T
JMAX
= 160°C,
θ
JA
= 190°C/W (S8)
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
V
S
=
±15V,
V
CM
= 0V, T
A
= 25°C, unless otherwise noted.
SYMBOL
V
OS
I
OS
I
B
e
n
PARAMETER
Input Offset Voltage
V
S
=
±5V
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
i
n
R
IN
Input Noise Current Density
Input Resistance
Differential Mode
Common Mode
Input Capacitance
V
S
=
±5V
Input Voltage Range (Note 4)
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Output Voltage Swing
Slew Rate
Gain-Bandwidth Product
Channel Separation
I
S
∆V
OS
∆I
B+
∆CMRR
∆PSRR
Supply Current per Amplifier
V
S
=
±5V
Offset Voltage Match
Noninverting Bias Current Match
Common Mode Rejection Match
Power Supply Rejection Match
Warmed Up (Note 2)
(Note 8)
(Note 8)
78
80
V
CM
= –10V to 13V
V
S
=
±4.5V
to
±
20V
V
O
=
±12V,
R
L
= 10k
V
O
=
±10V,
R
L
= 1k
R
L
= 10k
R
L
= 1k
R
L
≥
2k (Note 6)
f
O
= 100kHz
f
O
= 10Hz, V
O
=
±10V,
R
L
= 1k
13.0
–10.5
82
83
1000
500
±13.0
±12.0
2.4
3.3
Warmed Up (Note 2)
T
J
= 25°C (Note 5)
Warmed Up (Note 2)
T
J
= 25°C (Note 5)
0.1Hz to 10Hz
f
O
= 10Hz
f
O
= 1000Hz
f
O
= 10Hz, f
O
= 1kHz (Note 3)
CONDITIONS (Note 1)
MIN
TYP
0.60
0.65
2.5
0.7
4.0
1.5
2.4
17
6
1
10
14
10
13
1.5
2.0
13.5
–11.0
95
98
4500
3000
±13.8
±13.0
4.2
5.3
126
5.3
5.3
0.8
3
94
95
6.50
6.45
3.5
20
8
MAX
2.0
2.2
15
4
20
5
UNITS
mV
mV
pA
pA
pA
pA
µV
P-P
nV/√Hz
nV/√Hz
fA/√Hz
Ω
Ω
pF
pF
V
V
dB
dB
V/mV
V/mV
V
V
V/µs
MHz
dB
mA
mA
mV
pA
dB
dB
V
CM
= –10V to 13V
C
IN
V
CM
CMRR
PSRR
A
VOL
V
OUT
SR
GBW
2
U
W
U
U
W W
W
LT1169
ELECTRICAL CHARACTERISTICS
SYMBOL
V
OS
∆V
OS
∆Temp
I
OS
I
B
V
CM
CMRR
PSRR
A
VOL
V
OUT
SR
GBW
I
S
∆V
OS
∆I
B+
∆CMRR
∆PSRR
PARAMETER
Input Offset Voltage
Average Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Output Voltage Swing
Slew Rate
Gain-Bandwidth Product
Supply Current per Amplifier
V
S
=
±15V,
V
CM
= 0V, 0°C
≤
T
A
≤
70°C, (Note 9), unless otherwise noted.
MIN
q
q
q
q
q
q
q
CONDITIONS (Note 1)
V
S
=
±
5V
(Note 5)
TYP
0.7
0.8
20
10
180
MAX
3.2
3.4
50
50
400
UNITS
mV
mV
µV/°C
pA
pA
V
V
dB
dB
V/mV
V/mV
V
V
V/µs
MHz
12.9
–10.0
79
81
800
400
±12.5
±11.5
1.9
3
13.4
–10.8
94
97
3400
2400
±13.5
±12.7
4
4.2
5.3
5.3
1.5
5.5
6.55
6.50
5
50
V
CM
= –10V to 12.9V
V
S
=
±4.5V
to
±20V
V
O
=
±12V,
R
L
= 10k
V
O
=
±10V,
R
L
= 1k
R
L
= 10k
R
L
= 1k
R
L
≥
2k (Note 6)
f
O
= 100kHz
V
S
=
±5V
q
q
q
q
q
q
q
q
q
q
q
q
mA
mA
mV
pA
dB
dB
Offset Voltage Match
Noninverting Bias Current Match
Common Mode Rejection Match
Power Supply Rejection Match
(Note 8)
(Note 8)
q
q
74
77
93
93
V
S
=
±15V,
V
CM
= 0V, – 40°C
≤
T
A
≤
85°C, (Note 7), unless otherwise noted.
SYMBOL
V
OS
∆V
OS
∆Temp
I
OS
I
B
V
CM
CMRR
PSRR
A
VOL
V
OUT
SR
GBW
I
S
PARAMETER
Input Offset Voltage
V
S
=
±5V
Average Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Large-Signal Voltage Gain
Output Voltage Swing
Slew Rate
Gain-Bandwidth Product
Supply Current per Amplifier
V
S
=
±5V
V
CM
= –10V to 12.6V
V
S
=
±4.5V
to
±20V
V
O
=
±12V,
R
L
= 10k
V
O
=
±10V,
R
L
= 1k
R
L
= 10k
R
L
= 1k
R
L
≥
2k
f
O
= 100kHz
CONDITIONS (Note 1)
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
MIN
TYP
0.8
0.9
20
30
320
MAX
3.8
4.0
50
200
1200
UNITS
mV
mV
µV/°C
pA
pA
V
V
dB
dB
V/mV
V/mV
V
V
V/µs
MHz
12.6
–10.0
78
79
750
300
±12.5
±11.3
1.8
2.7
13.0
–10.5
93
96
3000
2000
±12.5
±12.0
3.8
4
5.30
5.25
6.55
6.50
mA
mA
3
LT1169
ELECTRICAL CHARACTERISTICS
V
S
=
±15V,
V
CM
= 0V, – 40°C
≤
T
A
≤
85°C, (Note 7), unless otherwise noted.
SYMBOL
∆V
OS
∆I
B+
∆CMRR
∆PSRR
PARAMETER
Offset Voltage Match
Noninverting Bias Current Match
Common Mode Rejection Match
Power Supply Rejection Match
(Note 8)
(Note 8)
CONDITIONS (Note 1)
q
q
q
q
MIN
TYP
1.8
10
MAX
6
180
UNITS
mV
pA
dB
dB
73
75
93
92
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Typical parameters are defined as the 60% yield of parameter
distributions of individual amplifiers, i.e., out of 100 LT1169s (200 op
amps) typically 120 op amps will be better than the indicated specification.
Note 2:
I
B
and I
OS
readings are extrapolated to a warmed-up temperature
from 25°C measurements and 45°C characterization data.
Note 3:
Current noise is calculated from the formula:
i
n
= (2qI
B
)
1/2
where q = 1.6
×
10
–19
coulomb. The noise of source resistors up to 200M
swamps the contribution of current noise.
Note 4:
Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 2.8mV.
Note 5:
This parameter is not 100% tested.
Note 6:
Slew rate is measured in A
V
= –1; input signal is
±7.5V,
output
measured at
±2.5V.
Note 7:
The LT1169 is designed, characterized and expected to meet these
extended temperature limits, but is not tested at – 40°C and 85°C.
Guaranteed I grade parts are available; consult factory.
Note 8:
∆CMRR
and
∆PSRR
are defined as follows:
(1) CMRR and PSRR are measured in
µV/V
on the individual
amplifiers.
(2) The difference is calculated between the matching sides in
µV/V.
(3) The result is converted to dB.
Note 9:
The LT1169 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed-up chip
temperature can be 10°C to 50°C higher than the ambient temperature.
TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Voltage Noise
50
T
A
= 25°C
V
S
=
±15V
510 OP AMPS TESTED
VOLTAGE NOISE (1µV/DIV)
40
30
RMS VOLTAGE NOISE (nV/√Hz)
PERCENT OF UNITS (%)
0
2
4
6
TIME (SEC)
4
U W
8
10
LT1169 • TPC01
1kHz Input Noise Voltage
Distribution
100
Voltage Noise vs Frequency
T
A
= 25°C
V
S
= ±15V
10
TYPICAL
1/f CORNER
60Hz
20
10
0
4.2 4.6 5.0 5.4 5.8 6.2 6.6 7.0 7.4 7.8 8.2
INPUT VOLTAGE NOISE (nV/√Hz)
LT1169 • TPC02
1
1
10
100
1k
FREQUENCY (Hz)
10k
LT1169 • TPC03
LT1169
TYPICAL PERFOR A CE CHARACTERISTICS
Voltage Noise vs Chip Temperature
10
30n
10n
3n
1n
300p
100p
30p
10p
3p
1p
0.3p
100 125
0
25
75
100
50
TEMPERATURE (°C)
125
OFFSET
CURRENT
BIAS
CURRENT
INPUT BIAS AND OFFSET CURRENTS (pA)
INPUT BIAS AND OFFSET CURRENTS (A)
VOLTAGE NOISE (AT 1kHz) (nV/√Hz)
V
S
= ±15V
9
8
7
6
5
4
3
2
–75 –50 –25 0
25 50 75
TEMPERATURE (°C)
Common Mode Limit
vs Temperature
V
+
0
COMMON MODE REJECTION RATIO (dB)
–0.5
POWER SUPPLY REJECTION RATIO (dB)
COMMON MODE LIMIT (V)
REFERRED TO POWER SUPPLY
–1.0
–1.5
–2.0
V
+
= 5V TO 20V
3.0
2.5
2.0
1.5
V
–
= – 5V TO – 20V
V
–
+1.0
–60
–20
60
100
20
TEMPERATURE (°C)
Voltage Gain vs Frequency
180
T
A
= 25°C
V
S
= ±15V
140
VOLTAGE GAIN (V/µV)
VOLTAGE GAIN (dB)
VOLTAGE GAIN (dB)
100
60
20
–20
0.01
1
10k
100
FREQUENCY (Hz)
U W
LT1169 • TPC04
Input Bias and Offset Currents
vs Chip Temperature
10
Input Bias and Offset Currents
Over the Common Mode Range
8
6
4
2
0
–2
–4
–6
–8
–10
–15
10
–10
0
5
–5
COMMON MODE RANGE (V)
15
BIAS CURRENT
OFFSET CURRENT
T
A
= 25°C
V
S
=
±15V
V
S
= ±15V
V
CM
= –10 TO 13V
LT1169 • TPC05*
LT1169 • TPC06
Common Mode Rejection Ratio
vs Frequency
120
100
80
60
40
20
0
T
A
= 25°C
V
S
=
±15V
Power Supply Rejection Ratio
vs Frequency
120
T
A
= 25°C
100
+PSRR
80
–PSRR
60
40
20
0
140
1k
10k
100k
1M
FREQUENCY (Hz)
10M
LT1169 • TPC08
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
LT1169 • TPC07
LT1169 • TPC09
Voltage Gain vs Chip Temperature
10
9
8
7
6
5
4
3
2
1
R
L
= 1k
R
L
=10k
V
S
= ±15V
V
O
= ±10V, R
L
= 1k
V
O
= ±12V, R
L
= 10k
50
40
30
20
Gain and Phase Shift
vs Frequency
T
A
= 25°C
V
S
= ±15V
C
L
= 10pF
60
80
PHASE SHIFT (DEG)
100
120
PHASE
140
GAIN
160
180
100
LT1169 • TPC12
10
0
–10
1M
100M
0
–75 –50 –25 0
25 50 75
CHIP TEMPERATURE (°C)
100 125
LT1169 • TPC11
0.1
1
10
FREQUENCY (MHz)
LT1169 • TPC10
5
NXP MCU
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