FEATURES
s
s
s
s
s
s
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LT1175
500mA Negative
Low Dropout Micropower
Regulator
DESCRIPTIO
The LT
®
1175 is a negative micropower low dropout regu-
lator. It features 45µA quiescent current, dropping to
10µA in shutdown. A new reference amplifier topology
gives precision DC characteristics along with the ability to
maintain good loop stability with an extremely wide range
of output capacitors. Very low dropout voltage and high
efficiency are obtained with a unique power transistor anti-
saturation design. Adjustable and fixed 5V versions are
available.
Several new features make the LT1175 very user-friendly.
The SHDN pin can interface directly to either positive or
negative logic levels. Current limit is user-selectable at
200mA, 400mA, 600mA and 800mA. The output can be
forced to reverse voltage without damage or latchup.
Unlike some earlier designs, the increase in quiescent
current during a dropout condition is actively limited.
The LT1175 has complete blowout protection with current
limiting, power limiting and thermal shutdown. Special
attention was given to the problem of high temperature
operation with micropower operating currents, preventing
output voltage rise under no-load conditions. The LT1175
is available in 8-pin PDIP and SO packages, 3-lead SOT-
223 as well as 5-pin surface mount DD and through-hole
TO-220 packages. The 8-pin SO package is specially
constructed for low thermal resistance.
Minimum Input-to-Output Voltage
1.0
INPUT-TO-OUTPUT VOLTAGE (V)
Stable with Wide Range of Output Capacitors
Operating Current: 45
µ
A
Shutdown Current: 10µA
Adjustable Current Limit
Positive or Negative Shutdown Logic
Low Voltage Linear Dropout Characteristics
Fixed 5V and Adjustable Versions
Tolerates Reverse Output Voltage
APPLICATIO S
s
s
s
s
s
s
Analog Systems
Modems
Instrumentation
A/D and D/A Converters
Interface Drivers
Battery-Powered Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
Typical LT1175 Connection
T
J
= 25°C
I
LIM2
, I
LIM4
TIED TO V
IN
0.8
+
C
IN
*
SHDN
–V
IN
INPUT
I
LIM2
LT1175-5
I
LIM4
GND
SENSE
OUT
+
C
OUT
≥
0.1µF
–5V
UP TO 500mA
0.6
0.4
0.2
*C
IN
IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM
INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION
1175 TA01
SECTION FOR DETAILS
0
0
0.1
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
0.6
0.7
U
U
U
1175 TA02
1
LT1175
ABSOLUTE
MAXIMUM
RATINGS
Input Voltage (Transient 1 sec, Note 11) ................ 25V
Input Voltage (Continuous) .................................... 20V
Input-to-Output Differential Voltage (Note 12) ........ 20V
5V SENSE Pin (with Respect to GND Pin) ...... 2V, – 10V
ADJ SENSE Pin
(with Respect to OUTPUT Pin) ................ 20V, – 0.5V
5V SENSE Pin
(with Respect to OUTPUT Pin) .................. 20V, – 7V
Output Reverse Voltage ............................................ 2V
SHDN Pin to GND Pin Voltage (Note 2) ..... 13.5V, – 20V
PACKAGE/ORDER INFORMATION
TOP VIEW
V
IN
1
I
LIM2
2
OUTPUT 3
SENSE 4
N8 PACKAGE
8-LEAD PDIP
8
7
6
5
V
IN
I
LIM4
SHDN
GND
ORDER
PART NUMBER
LT1175CN8
LT1175CN8-5
LT1175IN8
LT1175IN8-5
TAB
IS
INPUT
FRONT VIEW
5
4
3
2
1
Q PACKAGE
5-LEAD PLASTIC DD
SHDN
GND
INPUT
SENSE
OUTPUT
θ
JA
= 80°C/ W TO 120°C/W DEPENDING
ON PC BOARD LAYOUT
θ
JA
= 27°C/ W TO 60°C/W DEPENDING
ON PC MOUNTING. SEE DATA SHEET
FOR DETAILS
TOP VIEW
V
IN
1
I
LIM2
2
OUTPUT 3
SENSE 4
8
7
6
5
S8 PACKAGE
8-LEAD PLASTIC SO
V
IN
I
LIM4
SHDN
GND
θ
JA
= 60°C/ W TO 100°C/W DEPENDING
ON PC BOARD LAYOUT
PINS 1, 8 ARE INTERNALLY
CONNECTED TO DIE
ATTACH PADDLE FOR HEAT
SINKING. ELECTRICAL
CONTACT CAN BE MADE TO
EITHER PIN. FOR BEST
THERMAL RESISTANCE,
PINS 1, 8 SHOULD BE
CONNECTED TO AN
EXPANDED LAND THAT IS
OVER AN INTERNAL OR
BACKSIDE PLANE.
SEE APPLICATIONS
INFORMATION
ORDER
PART NUMBER
LT1175CS8
LT1175CS8-5
LT1175IS8
LT1175IS8-5
S8 PART MARKING
1175
11755
1175I
1175I5
Consult factory for Military grade parts.
The
q
denotes specifications which apply over the operating temperature
range, otherwise specifications are at T
A
= 25°C. V
OUT
= 5V, V
IN
= 7V, I
OUT
= 0, V
SHDN
= 3V, I
LIM2
and I
LIM4
tied to V
IN
, T
J
= 25°C,
unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as
absolute values except where polarity is not obvious.
PARAMETER
Feedback Sense Voltage
Output Voltage Initial Accuracy
Output Voltage Accuracy (All Conditions)
Quiescent Input Supply Current
CONDITIONS
Adjustable Part
Fixed 5V Part
Adjustable, Measured at 3.8V Sense
Fixed 5V
V
IN
– V
OUT
= 1V to V
IN
= 20V, I
OUT
= 0A to 500mA
P = 0 to P
MAX
, T
J
= T
MIN
to T
MAX
(Note 3)
V
IN
– V
OUT
≤
12V
MIN
3.743
4.93
TYP
3.8
5.0
0.5
0.5
1.5
45
q
ELECTRICAL CHARACTERISTICS
2
U
U
W
W W
U
W
(Note 1)
SHDN Pin to V
IN
Pin Voltage .......................... 30V, – 5V
Operating Junction Temperature Range
LT1175C .............................................. 0°C to 125°C
LT1175I .......................................... – 40°C to 125°C
Ambient Operating Temperature Range
LT1175C ................................................ 0°C to 70°C
LT1175I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER
PART NUMBER
LT1175CQ
LT1175CQ-5
LT1175IQ
LT1175IQ-5
TAB IS
INPUT
FRONT VIEW
1
2
3
GND
V
IN
OUTPUT
ORDER
PART NUMBER
LT1175CST-5
LT1175IST-5
ST PACKAGE
3-LEAD PLASTIC SOT-223
θ
JA
= 50°C/ W WITH BACKPLANE
AND 10cm
2
TOPSIDE LAND
SOLDERED TO TAB
FRONT VIEW
5
4
3
2
1
TAB IS
INPUT
SHDN
GND
INPUT
SENSE
OUTPUT
ORDER
PART NUMBER
LT1175CT
LT1175CT-5
LT1175IT
LT1175IT-5
T PACKAGE
5-LEAD PLASTIC TO-220
θ
JA
= 50°C/ W,
θ
JC
= 5°C/ W
q
MAX
3.857
5.075
1.5
1.5
2.5
65
80
UNITS
V
V
%
%
%
µA
µA
LT1175
ELECTRICAL CHARACTERISTICS
PARAMETER
GND Pin Current Increase with Load (Note 4)
Input Supply Current in Shutdown
Shutdown Thresholds (Note 9)
SHDN Pin Current (Note 2)
Output Bleed Current in Shutdown (Note 6)
SENSE Pin Input Current
Dropout Voltage (Note 7)
CONDITIONS
The
q
denotes specifications which apply over the operating temperature
range, otherwise specifications are at T
A
= 25°C. V
OUT
= 5V, V
IN
= 7V, I
OUT
= 0, V
SHDN
= 3V, I
LIM2
and I
LIM4
tied to V
IN
, T
J
= 25°C,
unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as
absolute values except where polarity is not obvious.
MIN
q
TYP
10
10
MAX
20
20
25
2.5
8
4
1
5
150
20
0.2
0.26
0.7
0.5
0.45
0.45
1300
975
650
325
0.015
0.35
0.1
0.2
1.25
UNITS
µA/mA
µA
µA
V
µA
µA
µA
µA
nA
µA
V
V
V
V
V
V
mA
mA
mA
mA
%/V
%
%/W
%/W
%
V
SHDN
= 0V
q
Either Polarity On SHDN Pin
V
SHDN
= 0V to 10V (Flows Into Pin)
V
SHDN
= – 15V to 0V (Flows Into Pin)
V
OUT
= 0V, V
IN
= 15V
(Adjustable Part Only, Current Flows Out of Pin)
(Fixed Voltage Only, Current Flows Out of Pin)
I
OUT
= 25mA
I
OUT
= 100mA
I
OUT
= 500mA
I
LIM2
Open, I
OUT
= 300mA
I
LIM4
Open, I
OUT
= 200mA
I
LIM2
, I
LIM4
Open, I
OUT
= 100mA
V
IN
– V
OUT
= 1V to 12V
I
LIM2
Open
I
LIM4
Open
I
LIM2
, I
LIM4
Open
V
IN
– V
OUT
= 1V to V
IN
= 20V
I
OUT
= 0mA to 500mA
P = 0 to P
MAX
(Notes 3, 8)
5-Pin Packages
8-Pin Packages
T
J
= 25°C to T
JMIN
, or 25°C to T
JMAX
q
q
0.8
4
1
0.1
1
75
12
0.1
0.18
0.5
0.33
0.3
0.26
800
600
400
200
0.003
0.1
0.04
0.1
0.25
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
Current Limit (Note 11)
520
390
260
130
Line Regulation (Note 10)
Load Regulation (Note 5, 10)
Thermal Regulation
Output Voltage Temperature Drift
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
SHDN pin maximum positive voltage is 30V with respect to
– V
IN
and 13.5V with respect to GND. Maximum negative voltage is – 20V
with respect to GND and – 5V with respect to – V
IN
.
Note 3:
P
MAX
= 1.5W for 8-pin packages, and 6W for 5-pin packages. This
power level holds only for input-to-output voltages up to 12V, beyond
which internal power limiting may reduce power. See Guaranteed Current
Limit curve in Typical Performance Characteristics section. Note that all
conditions must be met.
Note 4:
GND pin current increases because of power transistor base drive.
At low input-to-output voltages (< 1V) where the power transistor is in
saturation, GND pin current will be slightly higher. See Typical
Performance Characteristics.
Note 5:
With I
LOAD
= 0, at T
J
> 125°C, power transistor leakage could
increase higher than the 10µA to 25µA drawn by the output divider or fixed
voltage SENSE pin, causing the output to rise above the regulated value.
To prevent this condition, an internal active pull-up will automatically turn
on, but supply current will increase.
Note 6:
This is the current required to pull the output voltage to within 1V
of ground during shutdown.
Note 7:
Dropout voltage is measured by setting the input voltage equal to
the normal regulated output voltage and measuring the difference between
V
IN
and V
OUT
. For currents between 100mA and 500mA, with both I
LIM
pins tied to V
IN
, maximum dropout can be calculated from
V
DO
= 0.15 + 1.1Ω (I
OUT
).
Note 8:
Thermal regulation is a change in the output voltage caused by die
temperature gradients, so it is proportional to chip power dissipation.
Temperature gradients reach final value in less than 100ms. Output
voltage changes after 100ms are due to absolute die temperature changes
and reference voltage temperature coefficient.
Note 9:
The lower limit of 0.8V is guaranteed to keep the regulator in
shutdown. The upper limit of 2.5V is guaranteed to keep the regulator
active. Either polarity may be used, referenced to GND pin.
Note 10:
Load and line regulation are measured on a pulse basis with
pulse width of 20ms or less to keep chip temperature constant. DC
regulation will be affected by thermal regulation (Note 8) and chip
temperature changes. Load regulation specification also holds for currents
up to the specified current limit when I
LIM2
or I
LIM4
are left open.
Note 11:
Current limit is reduced for input-to-output voltage above 12V.
See the graph in Typical Performance Characteristics for guaranteed limits
above 12V.
Note 12:
Operating at very large input-to-output differential voltages
(>15V) with load currents less than 5mA requires an output capacitor with
an ESR greater than 1Ω to prevent low level output oscillations.
3
LT1175
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Current Limit
Characteristics
1.0
CURRENT LIMIT CHANGES ONLY SLIGHTLY
WITH TEMPERATURE SO CURVES ARE
REPRESENTATIVE OF ALL TEMPERATURES
I
LIM2
, I
LIM
TIED TO V
IN
0.6
I
LIM2
, I
LIM
TIED TO V
IN
0.5
0.4
0.3
0.2
I
LIM2
, I
LIM4
OPEN
0.1
0
3.80
I
LIM4
TIED TO V
IN
CURVES REPRE-
SENT MINIMUM
GUARANTEED
LIMITS AT ALL
TEMPERATURES
VOLTAGE (V)
0.8
CURRENT (A)
CURRENT (A)
0.6
I
LIM4
TIED TO V
IN
0.4
I
LIM2
TIED TO V
IN
0.2
I
LIM2
, I
LIM4
OPEN
0
5
15
0
20
25
10
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
1175 G01
Minimum Input-to-Output Voltage
1.0
INPUT-TO-OUTPUT VOLTAGE (V)
INPUT-TO-OUTPUT VOLTAGE (V)
0.8
T
J
= 25°C
V
IN
REDUCED
UNTIL OUTPUT
VOLTAGE
DROPS 1%
I
LIM2
, I
LIM4
OPEN
0.6
0.6
T
J
= 125°C
0.4
T
J
= 25°C
0.2
T
J
= –55°C
CURRENT (nA)
I
LIM2
TIED
TO V
IN
0.4
I
LIM4
TIED
TO V
IN
I
LIM2
, I
LIM4
TIED TO V
IN
0
0.1
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
0.6
0.7
0.2
0
Shutdown Input Current
25
2.5
20
INPUT CURRENT (µA)
15
T
J
= 25°C
T
J
= 125°C
10
T
J
= –55°C
5
1.5
NEGATIVE THRESHOLD
1.0
PIN CURRENT (µA)
THRESHOLD (V)
0
0
5
15
10
INPUT VOLTAGE (V)
20
25
1175 G07
4
U W
1175 G04
Guaranteed Current Limit
5.05
Output Voltage Temperature Drift
OUTPUT
FIXED 5V PART
5.00
4.95
I
LIM2
TIED TO V
IN
3.84
FEEDBACK VOLTAGE
ADJUSTABLE PART
5
10
15
20
25
0
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
1175 G02
3.76
50
75 100
0
25
–50 –25
JUNCTION TEMPERATURE (°C)
125
1175 G03
Minimum Input-to-Output Voltage
1.0
V
IN
REDUCED UNTIL OUTPUT
VOLTAGE DROPS 1%.
I
LIM2
, I
LIM4
TIED TO V
IN
100
SENSE Bias Current
(Adjustable Part)
0.8
80
60
40
20
0
0
0.1
0.5
0.2 0.3 0.4
OUTPUT CURRENT (A)
0.6
0.7
0
–50 –25
50
75
0
25
TEMPERATURE (°C)
100
125
1175 G05
1175 G06
Shutdown Thresholds
15
POSITIVE THRESHOLD
SHDN Pin Characteristics
V
IN
= 25V
CHARACTERISTICS DO NOT
CHANGE SIGNIFICANTLY WITH
TEMPERATURE, SO A SINGLE
CURVE IS SHOWN. POSITIVE
CURRENT FLOWS INTO
SHDN PIN
2.0
10
5
0
IF SHDN PIN IS NEGATIVE WITH
RESPECT TO INPUT VOLTAGE AND
INPUT VOLTAGE IS LESS THAN 15V,
NEGATIVE BREAKOVER POINT WILL
BE ABOUT 8V BELOW –V
IN
0.5
DEVICE IS OFF
BELOW THRESHOLD
0
–50 –25
25
50
75
0
TEMPERATURE (°C)
100
125
–5
–10
–25 –20 –15 –10 –5 0 5 10 15 20 25
SHUTDOWN TO GROUND VOLTAGE (V)
1175 G09
1175 G08
LT1175
TYPICAL PERFORMANCE CHARACTERISTICS
GND pin Current
20
GROUND PIN CURRENT (mA)
16
12
POWER
TRANSISTOR
IN DROPOUT
T
J
= –55°C
T
J
= 25°C
V
IN
– V
OUT
=
2V
T
J
= 25°C
REJECTION (dB)
8
4
0
0
0.1
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
PIN FUNCTIONS
SENSE Pin:
The SENSE pin is used in the adjustable
version to allow custom selection of output voltage, with
an external divider set to generate 3.8V at the SENSE pin.
Input bias current is typically 75nA flowing out of the pin.
Maximum forced voltage on the SENSE pin is 2V and –10V
with respect to GND pin.
The fixed 5V version utilizes the SENSE pin to give true
Kelvin connections to the load or to drive an external pass
transistor for higher output currents. Bias current out of
the 5V SENSE pin is approximately 12µA. Separating the
SENSE and OUTPUT pins also allows for a new loop
compensation technique described in the Applications
Information section.
SHDN Pin:
The SHDN pin is specially configured to allow
it to be driven from either positive voltage logic or with
negative only logic. Forcing the SHDN pin 2V either above
or below the GND pin will turn the regulator on. This makes
it simple to connect directly to positive logic signals for
active low shutdown. If no positive voltages are available,
the SHDN pin can be driven below the GND pin to turn the
regulator on.
When left open, the SHDN pin will default low
to a regulator “on” condition.
For all voltages below
absolute maximum ratings, the SHDN pin draws only a few
microamperes of current (see Typical Performance Char-
acteristics). Maximum voltage on the SHDN pin is 15V,
– 20V with respect to the GND pin and 35V, – 5V with
respect to the negative input pin.
I
LIM
Pins:
The two current limit pins are emitter sections
of the power transistor. When left open, they float several
hundred millivolts above the negative input voltage. When
shorted to the input voltage, they increase current limit by
a minimum of 200mA for I
LIM2
and 400mA for I
LIM4
. These
pins must be connected only to the input voltage, either
directly or through a resistor.
OUTPUT Pin:
The OUTPUT pin is the collector of the NPN
power transistor. It can be forced to the input voltage, to
ground or up to 2V positive with respect to ground without
damage or latchup (see Output Voltage Reversal in Appli-
cations Information section). The LT1175 has foldback
current limit, so maximum current at the OUTPUT pin is a
function of input-to-output voltage. See Typical Perfor-
mance Characteristics.
GND Pin:
The GND pin has a quiescent current of 45µA at
zero load current, increasing by approximately 10µA per
mA of output current. At 500mA output current, GND pin
current is about 5mA. Current flows into the GND pin.
U W
Ripple Rejection
100
V
OUT
= 12V
(ADJUSTABLE)
WITH 0.1µF ACROSS
DIVIDER RESISTOR
V
OUT
= 5V
(FIXED)
V
OUT
= 12V
(ADJUSTABLE)
80
60
40
20
V
IN
– V
OUT
≥
3V
T
J
= 25°C
0.6
0.7
I
OUT
= 100mA
V
IN
– V
OUT
= 2V
C
OUT
= 1µF TANT
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
0
1175 G10
RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF
INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN
25mA AND 500mA. LARGER OUTPUT CAPACITORS DO
NOT IMPROVE REJECTION FOR FREQUENCIES BELOW
50kHz. AT VERY LIGHT LOADS, REJECTION WILL
IMPROVE WITH LARGER OUTPUT CAPACITORS
1175 G11
U
U
U
5
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