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74HC574
Octal 3−State Noninverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
The 74HC574 is identical in pinout to the LS574. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
The HC574 is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
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MARKING
DIAGRAMS
20
20
1
TSSOP−20
DT SUFFIX
CASE 948E
1
HC574
A
L
Y
W
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
HC
574
ALYW
G
G
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
•
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
•
This is a Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 1
1
Publication Order Number:
74HC574/D
74HC574
OUTPUT
ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
OE
L
L
L
H
FUNCTION TABLE
Inputs
Clock
D
H
L
X
X
Output
Q
H
L
No Change
Z
L,H,
X
X = Don’t Care
Z = High Impedance
Figure 1. Pin Assignment
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
2
3
4
5
6
7
8
9
11
1
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
Figure 2. Logic Diagram
Design Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
Value
66.5
1.5
5.0
0.0075
Units
ea.
ns
mW
pJ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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2
74HC574
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
I
Latchup
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Latchup Performance
Oxygen Index: 30%
−
35%
Human Body Model (Note 2)
Machine Model (Note 3)
Above V
CC
and Below GND at 85_C (Note 4)
TSSOP
TSSOP
(Note 1)
Parameter
Value
*0.5
to
)7.0
*0.5
to V
CC
)0.5
*0.5
to V
CC
)0.5
$20
$35
$35
$75
$75
*65
to
)150
260
)150
128
450
Level 1
UL 94 V−0 @ 0.125 in
>2000
>200
$300
V
mA
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to EIA/JESD78.
5. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
, V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Parameter
(Referenced to GND)
(Referenced to GND)
Min
2.0
0
*55
0
0
0
Max
6.0
V
CC
)125
1000
500
400
Unit
V
V
_C
ns
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
ORDERING INFORMATION
Device
74HC574DTR2G
Package
TSSOP−20*
Shipping
†
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
74HC574
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
*55
to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
$0.1
$0.5
v85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
$1.0
$5.0
v125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
$1.0
$10
mA
mA
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
Minimum High−Level Output
Voltage
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
|
v
20
mA
V
in
= V
IH
V
V
OH
V
V
OL
V
in
= V
IL
|I
out
|
v
20
mA
V
in
= V
IL
V
I
in
I
OZ
Maximum Input Leakage
Current
Maximum Three−State
Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
I
CC
6.0
4.0
40
40
mA
7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
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