Hitachi Single-Chip Microcomputer
H8S/2194 Series, H8S/2194F-ZTAT
™
H8S/2194, HD6432194, HD64F2194,
H8S/2193, HD6432193
H8S/2192, HD6432192
H8S/2191, HD6432191
Hardware Manual
ADE-602-160
Ver 0.1
11/20/98
Hitachi, Ltd.
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole
or part of this document without Hitachi's permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents
or any other reasons during operation of the user's unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics
and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for
any intellectual property claims or other problems that may result from applications based on
the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.
Contents
Contents ..... .....................................................................................................i
Section 1 Overview ........................................................................................1
1.1 Overview ......................................................................................................................... 1
1.2 Internal Block Diagram.................................................................................................... 6
1.3 Pin Arrangement and Functions ....................................................................................... 7
1.3.1 Pin Arrangement................................................................................................. 7
1.3.2 Pin Functions ...................................................................................................... 8
Section 2 CPU................................................................................................15
2.1 Overview ......................................................................................................................... 15
2.1.1 Features .............................................................................................................. 15
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ................................... 16
2.1.3 Differences from H8/300 CPU ............................................................................ 17
2.1.4 Differences from H8/300H CPU ......................................................................... 17
2.2 CPU Operating Modes ..................................................................................................... 18
2.3 Address Space.................................................................................................................. 23
2.4 Register Configuration ..................................................................................................... 24
2.4.1 Overview ............................................................................................................ 24
2.4.2 General Registers................................................................................................ 25
2.4.3 Control Registers ................................................................................................ 26
2.4.4 Initial Register Values ........................................................................................ 27
2.5 Data Formats.................................................................................................................... 28
2.5.1 General Register Data Formats ........................................................................... 28
2.5.2 Memory Data Formats ........................................................................................ 30
2.6 Instruction Set.................................................................................................................. 31
2.6.1 Overview ............................................................................................................ 31
2.6.2 Instructions and Addressing Modes..................................................................... 31
2.6.3 Table of Instructions Classified by Function ....................................................... 33
2.6.4 Basic Instruction Formats ................................................................................... 43
2.6.5 Notes on Use of Bit-Manipulation Instructions.................................................... 44
2.7 Addressing Modes and Effective Address Calculation...................................................... 44
2.7.1 Addressing Mode................................................................................................ 44
2.7.2 Effective Address Calculation............................................................................. 47
2.8 Processing States.............................................................................................................. 51
2.8.1 Overview ............................................................................................................ 51
2.8.2 Reset State.......................................................................................................... 52
2.8.3 Exception-Handling State ................................................................................... 53
2.8.4 Program Execution State..................................................................................... 54
Rev. 0.1, 11/98, page i of xviii
2.8.5 Power-Down State .............................................................................................. 54
2.9 Basic Timing ................................................................................................................... 55
2.9.1 Overview ............................................................................................................ 55
2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 55
2.9.3 On-Chip Supporting Module Access Timing....................................................... 56
Section 3 MCU Operating Modes .................................................................... 57
3.1 Overview ......................................................................................................................... 57
3.1.1 Operating Mode Selection .................................................................................. 57
3.1.2 Register Configuration........................................................................................ 57
3.2 Register Descriptions ....................................................................................................... 58
3.2.1 Mode Control Register (MDCR)......................................................................... 58
3.2.2 System Control Register (SYSCR)...................................................................... 58
3.3 Operating Mode Descriptions........................................................................................... 59
3.3.1 Mode 1 ............................................................................................................... 59
3.4 Address Map in Each Operating Mode............................................................................. 60
Section 4 Power-Down State.......................................................................... 63
4.1 Overview ......................................................................................................................... 63
4.1.1 Register Configuration........................................................................................ 67
4.2 Register Descriptions ....................................................................................................... 67
4.2.1 Standby Control Register (SBYCR) .................................................................... 67
4.2.2 Low-Power Control Register (LPWRCR) ........................................................... 69
4.2.3 Timer Register A (TMA) .................................................................................... 71
4.2.4 Module Stop Control Register (MSTPCR) .......................................................... 73
4.3 Medium-Speed Mode....................................................................................................... 74
4.4 Sleep Mode...................................................................................................................... 75
4.4.1 Sleep Mode......................................................................................................... 75
4.4.2 Clearing Sleep Mode .......................................................................................... 75
4.5 Module Stop Mode .......................................................................................................... 76
4.5.1 Module Stop Mode ............................................................................................. 76
4.6 Standby Mode.................................................................................................................. 77
4.6.1 Standby Mode..................................................................................................... 77
4.6.2 Clearing Standby Mode ...................................................................................... 77
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode .......................... 77
4.7 Watch Mode .................................................................................................................... 79
4.7.1 Watch Mode ....................................................................................................... 79
4.7.2 Clearing Watch Mode......................................................................................... 79
4.8 Subsleep Mode................................................................................................................. 80
4.8.1 Subsleep Mode ................................................................................................... 80
4.8.2 Clearing Subsleep Mode ..................................................................................... 80
4.9 Subactive Mode ............................................................................................................... 81
4.9.1 Subactive Mode .................................................................................................. 81
Rev. 0.1, 11/98, page ii of xviii
4.9.2 Clearing Subactive Mode.................................................................................... 81
4.10 Direct Transition ............................................................................................................ 82
4.10.1 Overview of Direct Transition........................................................................... 82
Section 5 Exception Handling ........................................................................83
5.1 Overview ......................................................................................................................... 83
5.1.1 Exception Handling Types and Priority............................................................... 83
5.1.2 Exception Handling Operation............................................................................ 84
5.1.3 Exception Sources and Vector Table................................................................... 84
5.2 Reset................................................................................................................................ 86
5.2.1 Overview ............................................................................................................ 86
5.2.2 Reset Sequence................................................................................................... 86
5.2.3 Interrupts after Reset........................................................................................... 87
5.3 Interrupts ......................................................................................................................... 88
5.4 Trap Instruction ............................................................................................................... 89
5.5 Stack Status after Exception Handling ............................................................................. 90
5.6 Notes on Use of the Stack ................................................................................................ 91
Section 6 Interrupt Controller...........................................................................93
6.1 Overview ......................................................................................................................... 93
6.1.1 Features .............................................................................................................. 93
6.1.2 Block Diagram.................................................................................................... 94
6.1.3 Pin Configuration................................................................................................ 95
6.1.4 Register Configuration........................................................................................ 95
6.2 Register Descriptions ....................................................................................................... 96
6.2.1 System Control Register (SYSCR)...................................................................... 96
6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)............................................ 97
6.2.3 IRQ Enable Register (IENR)............................................................................... 98
6.2.4 IRQ Edge Select Registers (IEGR)...................................................................... 99
6.2.5 IRQ Status Register (IRQR)................................................................................ 100
6.2.6 Port Mode Register (PMR1)................................................................................ 101
6.3 Interrupt Sources.............................................................................................................. 102
6.3.1 External Interrupts .............................................................................................. 102
6.3.2 Internal Interrupts ............................................................................................... 104
6.3.3 Interrupt Exception Vector Table........................................................................ 104
6.4 Interrupt Operation........................................................................................................... 107
6.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 107
6.4.2 Interrupt Control Mode 0 .................................................................................... 109
6.4.3 Interrupt Control Mode 1 .................................................................................... 111
6.4.4 Interrupt Exception Handling Sequence .............................................................. 114
6.4.5 Interrupt Response Times ................................................................................... 115
6.5 Usage Notes..................................................................................................................... 116
6.5.1 Contention between Interrupt Generation and Disabling ..................................... 116
Rev. 0.1, 11/98, page iii of xviii
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