024AV33
CY7C1024AV33
128K x 24 Static RAM
Features
• High speed
— t
AA
= 10 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE1, CE2, CE3 and OE
options
Writing to the device is accomplished by taking Chip Enable
(CE1, CE2, CE3) active and Write Enable (WE) inputs LOW.
Data on the 24 I/O pins (I/O
0
through I/O
23
) is then written into
the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE1, CE2, CE3) active and Output Enable (OE) LOW
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The 24 input/output pins (I/O
0
through I/O
23
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW).
The CY7C1024AV33 is available in a standard 119-ball BGA
package and a 100-pin TQFP package.
Functional Description
[1]
The CY7C1024AV33 is a high-performance CMOS static RAM
organized as 131,072 words by 24 bits. Easy memory expan-
sion is provided by an active LOW CE1, CE3, active HIGH
CE2, an active LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Functional Block Diagram
V
CC
V
SS
A
0
ADDRESS BUFFER
ROW DECODER
DQ
0
MEMORY ARRAY
128K X 24
I/O BUFFER
DQ
23
A
16
COLUMN
DECODER
CONTROL
CE#
CE1#
CE2
WE#
OE#
Selection Guide
7C1024AV33-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
10
275
15
7C1024AV33-12
12
250
15
7C1024AV33-15
15
225
15
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05149 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised November 13, 2002
CY7C1024AV33
Pin Configurations
(continued)
100-pin TQFP
Top View
NC
NC
A11
A12
A13
A14
A15
CE2
VCC
VSS
CE1#
CE#
A16
A5
A4
A3
NC
NC
NC
NC
NC
VCC
VSS
DQ16
DQ17
VSS
VCC
DQ18
DQ19
VSS
VCC
DQ20
DQ21
VCC
NC
NC
VSS
DQ22
DQ23
VCC
VSS
DQ12
DQ13
VCC
VSS
DQ14
DQ15
VCC
VSS
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VCC
VSS
DQ0
DQ1
VSS
VCC
DQ2
DQ3
VSS
VCC
DQ4
DQ5
VCC
NC
NC
VSS
DQ6
DQ7
VCC
VSS
DQ8
DQ9
VCC
VSS
DQ10
DQ11
VCC
VSS
NC
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
Note:
2. Minimum Voltage is = –2.0V for pulse durations of less than 20 ns.
NC
NC
NC
NC
A10
A9
A8
A7
OE#
VSS
VCC
WE#
A6
A0
A1
A2
NC
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V ±10%
3.3V ±10%
Document #: 38-05149 Rev. *B
Page 3 of 11
CY7C1024AV33
Switching Characteristics
[5]
Over the Operating Range
7C1024AV33-10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE active to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE active to Low Z
[7]
CE inactive to High Z
[6, 7]
CE active to Power-Up
CE inactive to Power-Down
Write Cycle Time
CE active to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
10
8
7
0
0
7
5
0
3
5
0
10
12
9
8
0
0
8
6
0
3
6
3
5
0
12
15
9
8
0
0
8
6
0
3
6
0
5
3
6
0
15
3
10
5
0
6
3
6
10
10
3
12
6
0
6
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
[3]
Min.
Max.
7C1024AV33-12
Min.
Max.
7C1024AV33-15
Min.
Max.
Unit
WRITE CYCLE
[8, 9]
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05149 Rev. *B
Page 5 of 11
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