LT1640L/LT1640H
Negative Voltage
Hot Swap Controller
FEATURES
s
s
s
s
s
s
s
DESCRIPTION
The LT
®
1640L/LT1640H is an 8-pin, negative voltage Hot
Swap
TM
controller that allows a board to be safely inserted
and removed from a live backplane. Inrush current is
limited to a programmable value by controlling the gate
voltage of an external N-channel pass transistor. The pass
transistor is turned off if the input voltage is less than the
programmable undervoltage threshold or greater than the
overvoltage threshold. A programmable electronic circuit
breaker protects the system against shorts. The PWRGD
(LTC1640L) or PWRGD (LTC1640H) signal can be used to
directly enable a power module. The LT1640L is designed
for modules with a low enable input and the LT1640H for
modules with a high enable input.
The LT1640L/LT1640H is available in 8-pin PDIP and SO
packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
Allows Safe Board Insertion and Removal
from a Live – 48V Backplane
Operates from –10V to – 80V
Programmable Inrush Current
Programmable Electronic Circuit Breaker
Programmable Overvoltage Protection
Programmable Undervoltage Lockout
Power Good Control Output
APPLICATIONS
s
s
s
Central Office Switching
– 48V Distributed Power Systems
Negative Power Supply Control
TYPICAL APPLICATION
Input Inrush Current
GND
R4
562k
1%
UV = 37V
R5
9.09k
1%
R6
10k
1%
8
V
DD
3
UV
LT1640L
2
OV
V
EE
4
SENSE
5
C1
33nF
24V
GATE
6
R2
10Ω
5%
R3
10k
5%
C2
3.3nF
100V
2
1
C3
0.1µF
100V
V
IN+
ON/OFF
9
V
OUT+
8
SENSE
+
7
TRIM
6
SENSE
–
–
5
–
V
OUT
V
IN
LUCENT
JW050A1-E
5V
DRAIN
7
PWRGD
1
CONTACT
BOUNCE
OV = 71V
R1
0.02Ω
5%
– 48V
Q1
IRF530
+
C4
100µF
100V
4
+
C5
100µF
16V
1640 F07b
1640 TA01
U
U
U
1
LT1640L/LT1640H
ABSOLUTE
MAXIMUM
RATINGS
U
W W
U
W
(Note 1), All Voltages Referred to V
EE
Supply Voltage (V
DD
– V
EE
) .................... – 0.3V to 100V
DRAIN, PWRGD, PWRGD Pins ............... – 0.3V to 100V
SENSE, GATE Pins .................................... – 0.3V to 20V
UV, OV Pins .............................................. – 0.3V to 60V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LT1640LC/LT1640HC ............................. 0°C to 70°C
LT1640LI/LT1640HI .......................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
PACKAGE/ORDER I FOR ATIO
TOP VIEW
PWRGD 1
OV 2
UV 3
V
EE
4
N8 PACKAGE
8-LEAD PDIP
8
7
6
5
V
DD
DRAIN
GATE
SENSE
ORDER PART
NUMBER
LT1640LCN8
LT1640LCS8
LT1640LIN8
LT1640LIS8
S8 PART MARKING
1640L
1640LI
PWRGD 1
OV 2
UV 3
V
EE
4
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 120°C/W (N8)
T
JMAX
= 125°C,
θ
JA
= 150°C/W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL
DC
V
DD
I
DD
V
CB
I
PU
I
PD
I
SENSE
∆V
GATE
V
UVH
V
UVL
V
UVHY
I
INUV
V
OVH
V
OVL
V
OVHY
I
INOV
Supply Voltage
Supply Current
Circuit Breaker Trip Voltage
GATE Pin Pull-Up Current
GATE Pin Pull-Down Current
SENSE Pin Current
External Gate Drive
UV Pin High Threshold Voltage
UV Pin Low Threshold Voltage
UV Pin Hysteresis
UV Pin Input Current
OV Pin High Threshold Voltage
OV Pin Low Threshold Voltage
OV Pin Hysteresis
OV Pin Input Current
V
OV
= V
EE
V
UV
= V
EE
PARAMETER
CONDITIONS
(Note 2), V
DD
= 48V, V
EE
= 0V, T
A
= 25°C unless otherwise noted.
MIN
q
UV = 3V, OV = V
EE
, SENSE = V
EE
V
CB
= (V
SENSE
– V
EE
)
Gate Drive On, V
GATE
= V
EE
Any Fault Condition
V
SENSE
= 50mV
(V
GATE
– V
EE
), 15V
≤
V
DD
≤
80V
(V
GATE
– V
EE
), 10V
≤
V
DD
< 15V
UV Low to High Transition
UV High to Low Transition
OV Low to High Transition
OV High to Low Transition
2
U
TOP VIEW
8
7
6
5
V
DD
DRAIN
GATE
SENSE
W
ORDER PART
NUMBER
LT1640HCN8
LT1640HCS8
LT1640HIN8
LT1640HIS8
S8 PART MARKING
1640H
1640HI
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 120°C/W (N8)
T
JMAX
= 125°C,
θ
JA
= 150°C/W (S8)
TYP
MAX
80
UNITS
V
mA
mV
µA
mA
µA
V
V
V
V
mV
µA
V
V
mV
µA
10
1.3
40
– 30
24
50
– 45
50
– 20
13.5
8
1.243
1.223
20
– 0.02
1.198
1.165
1.223
1.203
20
– 0 .03
q
q
q
5
60
– 60
70
18
15
1.272
1.247
– 0.5
1.247
1.232
– 0.5
q
q
q
q
10
6
1.213
1.198
q
q
q
q
LT1640L/LT1640H
ELECTRICAL CHARACTERISTICS
SYMBOL
V
PG
V
PGHY
V
OL
R
OUT
AC
t
PHLOV
t
PHLUV
t
PLHOV
t
PLHUV
t
PHLSENSE
t
PHLPG
t
PLHPG
OV High to GATE Low
UV Low to GATE Low
OV Low to GATE High
UV High to GATE High
SENSE High to Gate Low
DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD – DRAIN) High
DRAIN High to PWRGD High
DRAIN High to (PWRGD – DRAIN) Low
PARAMETER
Power Good Threshold
Power Good Threshold Hysteresis
Output Low Voltage
Power Good Output Impedance
V
DD
= 48V, V
EE
= 0V, T
A
= 25°C unless otherwise noted.
MIN
1.1
q
q
CONDITIONS
V
DRAIN
– V
EE
, High to Low Transition
PWRGD (LT1640L), I
OUT
= 1mA,
(V
DRAIN
– V
EE
) < V
PG
PWRGD (LT1460H), (V
DRAIN
– V
EE
) < V
PG
Figures 1, 2
Figures 1, 3
Figures 1, 2
Figures 1, 3
Figures 1, 4
(LT1640L) Figures 1, 5
(LT1640H) Figures 1, 5
(LT1640L) Figures 1, 5
(LT1640H) Figures 1, 5
TYP
1.4
0.4
0.48
MAX
2.0
0.8
UNITS
V
V
V
kΩ
µs
µs
µs
µs
2
6.5
1.7
1.5
5.5
6.5
2
3
0.5
0.5
0.5
0.5
4
µs
µs
µs
µs
µs
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V
EE
unless otherwise
specified.
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
1.8
1.7
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1.6
1.5
1.4
1.3
1.2
1.1
0
0
20
80
60
SUPPLY VOLTAGE (V)
40
100
1640 G01
GATE VOLTAGE (V)
U W
Supply Current vs Temperature
1.6
1.5
1.4
1.3
1.2
1.1
7
15
14
13
12
11
10
9
8
Gate Voltage vs Supply Voltage
1.0
– 50
– 25
0
25
50
TEMPERATURE (°C)
75
100
1640 G02
6
0
20
80
60
40
SUPPLY VOLTAGE (V)
100
1640 G03
3
LT1640L/LT1640H
TYPICAL PERFOR A CE CHARACTERISTICS
Gate Voltage vs Temperature
15.0
14.5
14.0
13.5
13.0
12.5
12.0
– 50
TRIP VOLTAGE (mV)
GATE PULL-UP CURRENT (µA)
GATE VOLTAGE (V)
– 25
25
50
0
TEMPERATURE (°C)
Gate Pull-Down Current
vs Temperature
55
PWRGD OUTPUT LOW VOLTAGE (V)
GATE PULL-DOWN CURRENT (mA)
OUTPUT IMPEDANCE (Ω)
52
49
46
43
40
– 50
– 25
0
50
25
TEMPERATURE (°C)
PIN FUNCTIONS
PWRGD/PWRGD (Pin 1):
Power Good Output Pin. This pin
will toggle when V
DRAIN
is within V
PG
of V
EE
. This pin can
be connected directly to the enable pin of a power module.
When the DRAIN pin of the LT1640L is above V
EE
by more
than V
PG
, the PWRGD pin will be high impedance, allowing
the pull-up current of the module’s enable pin to pull the
pin high and turn the module off. When V
DRAIN
drops
below V
PG
, the PWRGD pin sinks current to V
EE
, pulling
the enable pin low and turning on the module.
When the DRAIN pin of the LT1640H is above V
EE
by more
than V
PG
, the PWRGD pin will sink current to the DRAIN
pin which pulls the module’s enable pin low, forcing it off.
When V
DRAIN
drops below V
PG
, the PWRGD sink current
is turned off and a 5k resistor is connected between
PWRGD and DRAIN, allowing the module’s pull-up cur-
rent to pull the enable pin high and turn on the module.
OV (Pin 2):
Analog Overvoltage Input. When OV is pulled
above the 1.223V low to high threshold, an overvoltage
condition is detected and the GATE pin will be immediately
pulled low. The GATE pin will remain low until OV drops
below the 1.203V high to low threshold.
4
U W
75
1640 G04
Circuit Breaker Trip Voltage
vs Temperature
55
54
53
52
51
50
49
48
– 50
48
47
46
45
44
43
42
41
Gate Pull-Up Current
vs Temperature
100
– 25
50
0
25
TEMPERATURE (°C)
75
100
1640 G05
40
– 50
– 25
0
25
50
TEMPERATURE (°C)
75
100
1640 G06
PWRGD Output Low Voltage
vs Temperature (LT1640L)
0.5
8
7
6
5
4
3
PWRGD Output Impedance
vs Temperature (LT1640H)
0.4
0.3
0.2
0.1
75
100
1640 G07
0
– 50
– 25
25
50
0
TEMPERATURE (°C)
75
100
1640 G08
2
– 50
– 25
0
25
50
TEMPERATURE (°C)
75
100
1640 G09
U
U
U
LT1640L/LT1640H
PIN FUNCTIONS
UV (Pin 3):
Analog Undervoltage Input. When UV is
pulled below the 1.223V high to low threshold, an under-
voltage condition is detected and the GATE pin will be
immediately pulled low. The GATE pin will remain low
until UV rises above the 1.243 low to high threshold.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and
a normal power-up sequence will occur.
V
EE
(Pin 4):
Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
SENSE (Pin 5):
Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between V
EE
and
SENSE, the circuit breaker will trip when the voltage
across the resistor exceeds 50mV. Noise spikes of less
than 2µs are filtered out and will not trip the circuit
breaker.
If the circuit breaker trip current is set to twice the normal
operating current, only 25mV is dropped across the
sense resistor during normal operation. To disable the
circuit breaker, V
EE
and SENSE can be shorted together.
GATE (Pin 6):
Gate Drive Output for the External
N-Channel. The GATE pin will go high when the following
start-up conditions are met: the UV pin is high, the OV pin
is low and (V
SENSE
– V
EE
) < 50mV. The GATE pin is pulled
high by a 45µA current source and pulled low with a
50mA current source.
DRAIN (Pin 7):
Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel and the V
–
pin
of the power module. When the DRAIN pin is below V
PG
,
the PWRGD or PWRGD pin will toggle.
V
DD
(Pin 8):
Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V
+
pin of the power module. The input supply voltage
ranges from 10V to 80V.
BLOCK DIAGRA
UV
REF
OV
–+
V
EE
SENSE
+
–
W
+
+
–
–
U
U
U
V
DD
V
CC
AND
REFERENCE
GENERATOR
V
CC
REF
OUTPUT
DRIVE
PWRGD/PWRGD
50mV
LOGIC
AND
GATE DRIVE
+
+
–
V
EE
V
PG
–
1640 BD
GATE
DRAIN
5
FPGA/CPLD
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