notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08
1
IS43R16320B
IC43R16320B
Block Diagram
CK
/CK
CKE
Clock
generator
Bank 3
Bank 2
Bank 1
A0 to A12, BA0, BA1
Mode
register
Row
address
buffer
and
refresh
counter
Row decoder
Memory cell array
Bank 0
Sense amp.
Command decoder
/CS
/RAS
/CAS
/WE
Column
address
buffer
and
burst
counter
Column decoder
Control logic
Data control circuit
Latch circuit
DQS
CK, /CK
DLL
Input & Output buffer
DM
DQ
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08
IS43R16320B
IC43R16320B
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DDQ
LDQS
NC
VDD
DNU
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTIONS
A0-A12
A0-A9
BA0, BA1
DQ0 to DQ15
CK,
CK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDM, UDM
LDQS, UDQS
V
DD
Vss
V
DDQ
Vss
Q
V
REF
DNU
NC
Write Enable
x16 Input Mask
Data Strobe
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
Input Reference Voltage
Do Not Use
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08
3
IS43R16320B
IC43R16320B
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A9, and A11 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Row address
AX0 to AX12
Column
address
AY0 to AY9
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = high when read or write
command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank 0
Bank 1
Bank 2
Bank 3
L
H
L
H
BA1
L
L
H
H
Remark: H: VIH. L: VIL.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08
IS43R16320B
IC43R16320B
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is high, the next CK rising edge is valid. If CKE is
low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when
the CKE is driven low and exited when it resumes to high. CKE must be maintained high throughout read or write
access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
LDM and UDM (input pins)
DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and
VREF. DMs provide the byte mask function. When DM = high, the data input at the same timing are masked while
the internal burst counter will be count up. In
×16
products, LDM controls the lower byte (DQ0 to DQ7) and UDM
controls the upper byte (DQ8 to DQ15) of write data.
DQ0 to DQ15 (input/output pins)
Data is input to and output from these pins (DQ0 to DQ15).
LDQS and UDQS (input and output pins)
DQS provides the read data strobes (as output) and the write data strobes (as input). In
×16
products, LDQS is the
lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
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