3
fax id: 2046
PRELIMINARY
CYM1836V33
128K x 32 3.3V Static RAM Module
Features
• High-density 3.3V 4-megabit SRAM module
• 32-bit standard footprint supports densities from 16K
x 32 through 1M x 32
• High-speed CMOS SRAMs
• Access time of 25 ns
— Low active power 1.6W (max.) at 20 ns
• 2.0V Data Retention (I
CCDRL
= 0.8 mA, max.)
• SMD technology
• TTL-compatible inputs and outputs
• Available in 64-pin SIMM, 64-pin ZIP format or 72-pin
SIMM format.
lects (CS
1
, CS
2
, CS
3
, CS
4
) are used to independently enable
the four bytes. Reading or writing can be executed on individ-
ual bytes or any combination of multiple bytes through proper
use of selects.
Writing to each byte is accomplished when the appropriate
chip select (CS) and write enable (WE) inputs are both LOW.
Data on the input/output pins (I/O) is written into the mem-
ory location specified on the address pins (A
0
through A
16
).
Reading the device is accomplished by taking the chip select
(CS) LOW while write enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pins will appear on the data in-
put/output pins (I/O).
The data input/output pins stay at the high-impedance state
when write enable is LOW or the appropriate chip selects are
HIGH.
Two pins (PD
0
and PD
1
) are used to identify module mem-
ory density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
72-pin SIMM
Top View
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
NC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Functional Description
The CYM1836V33 is a 3.3V high-performance 4-megabit stat-
ic RAM module organized as 128K words by 32 bits. This mod-
ule is constructed from four 128K x 8 SRAMs in SOJ packages
mounted on an epoxy laminate board with pins. Four chip se-
Logic Block Diagram
Pin Configurations
64-pin ZIP/SIMM
Top View
PD
0
−OPEN
PD
1
−OPEN
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
1836V33–2
A
0
−
A
16
OE
WE
17
PD
0
-
PD
1
-
PD
2
-
PD
3
-
OPEN
OPEN
OPEN
GND
128K x 8
SRAM
CS
1
128K x 8
SRAM
CS
2
128K x 8
SRAM
CS
3
128K x 8
SRAM
CS
4
4
I/O
0
−I/O
7
4
I/O
8
−I/O
15
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
A
18
NC
4
I/O
16
−I/O
23
4
I/O
24
−I/O
31
1836V33–1
1836V33–3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
April 29, 1998
PRELIMINARY
Selection Guide
1836V33–15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Shaded area contains advance information.
CYM1836V33
1836V33–20
20
480
20
1836V33–25 1836V33–30 1836V33–35 1836V33–45
25
440
20
30
440
20
35
440
20
45
440
20
15
520
20
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –55°C to +125°C
Ambient Temperature with
Power Applied ............................................... –10°C to +85°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .....................................–0.5V to +V
CC
+ 0.5V
DC Input Voltage..................................–0.5V to +V
CC
+ 0.5V
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
3.3V
±
300mV
Electrical Characteristics
Over the Operating Range
1836V33–15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply Current
Automatic CS Power-Down
Current
[1]
Automatic CS Power-Down
Current
[1]
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., I
OUT
= 0 mA, CS < V
IL
V
CC
= Max., CS > V
IH
,
Min. Duty Cycle = 100%
V
CC
= Max., CS > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–4
–5
Min.
2.4
0.4
V
CC
+0.3
0.8
+4
+5
520
100
20
2.2
–0.3
–4
–5
Max.
1836V33–20, 25,
30, 35, 45
Min.
2.4
0.4
V
CC
+0.3
0.8
+4
+5
480 (20ns)
440
80
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Shaded area contains advance information.
Capacitance
[2]
Parameter
C
IN
C
OUT
Description
Input Capacitance
[3]
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
24
8
Unit
pF
pF
Notes:
1. A pull-up resistor to V
CC
on the CS input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
2. Tested on a sample basis.
3. 20 pF on CS, 40 pF all others.
2
PRELIMINARY
AC Test Loads and Waveforms
R1 481
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
R1 481
Ω
3.0V
90%
GND
< 5 ns
1836V33–4
CYM1836V33
ALL INPUT PULSES
90%
10%
< 5 ns
1836V33–5
10%
(a)
(b)
Equivalent to:
OUTPUT
THÉ VENIN EQUIVALENT
167Ω
1.73V
Switching Characteristics
Over the Operating Range
[4]
1836V33–15 1836V33–20 1836V33–25 1836V33–30 1836V33–35 1836V33–45
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
Read Cycle
Time
Address to Data
Valid
Output Hold
from Address
Change
CS LOW to Data
Valid
OE LOW to Data
Valid
OE LOW to
Low Z
OE HIGH to
High Z
CS LOW to
Low Z
[5]
CS HIGH to High
Z
[5, 6]
3
7
0
7
3
10
3
15
15
3
20
20
3
25
25
3
30
30
3
35
35
3
45
45
ns
ns
ns
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
15
7
0
20
8
0
8
3
25
8
0
10
3
10
30
10
0
11
3
13
35
12
0
12
3
15
45
15
ns
ns
ns
15
ns
ns
18
ns
Shaded area contains advance information.
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. At any given temperature and voltage condition, t
HZCS
is less than t
LZCS
for any given device. These parameters are guaranteed by design and not 100% tested.
6. t
HZCS
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
±500
mV from steady-state voltage.
3
PRELIMINARY
Switching Characteristics
Over the Operating Range
[4]
(continued)
CYM1836V33
1836V33–15 1836V33–20 1836V33–25 1836V33–30 1836V33–35 1836V33–45
Parameter
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
Write Cycle
Time
CS LOW to Write
End
Address Set-Up
to Write End
Address Hold
from Write End
Address Set-Up
to Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
WE HIGH to Low
Z
WE LOW to High
Z
[6]
Min.
15
12
12
0
0
12
7
0
3
0
7
Max.
Min.
20
15
15
0
0
15
10
0
3
0
8
Max.
Min.
25
15
15
0
0
15
10
0
3
0
10
Max.
Min.
30
18
18
0
0
18
13
0
3
0
15
Max.
Min.
35
20
20
0
0
20
15
0
3
0
15
Max.
Min.
45
25
25
0
0
25
20
0
3
0
18
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
[7]
Shaded area contains advance information.
Switching Waveforms
Read Cycle No.1
[8, 9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1836V33–6
Read Cycle No. 2
[8, 10]
CS
t
ACS
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
t
LZCS
DATA VALID
1836V33–7
t
RC
t
HZOE
t
HZCS
HIGH
IMPEDANCE
Notes:
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
8. WE is HIGH for read cycle.
9. Device is continuously selected, CS = V
IL
and OE= V
IL
.
10. Address valid prior to or coincident with CS transition LOW.
4
PRELIMINARY
Switching Waveforms
(continued)
Write Cycle No.1 (WE Controlled)
[7]
t
WC
ADDRESS
t
SCS
CS
t
SA
WE
t
SD
DATA IN
DATA VALID
t
HZWE
DATA OUT
DATA UNDEFINED
t
LZWE
HIGH IMPEDANCE
t
HD
t
AW
t
PWE
t
HA
CYM1836V33
1836V33–8
Write Cycle No. 2 (CS Controlled)
[7, 11]
t
WC
ADDRESS
t
SA
CS
t
AW
t
PWE
WE
t
SD
DATA IN
DATA VALID
t
HZWE
DATA OUT
HIGH IMPEDANCE
DATA UNDEFINED
1836V33–9
t
SCS
t
HA
t
HD
Note:
11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CS
N
H
L
L
L
WE
X
H
L
H
OE
X
L
X
H
Input/Outputs
High Z
Data Out
Data In
High Z
Read
Write
Deselect
Mode
Deselect/Power-Down
5
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